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/external/libcxx/lib/abi/
Dx86_64-unknown-linux-gnu.abilist2 {'is_defined': True, 'name': '_ZNKSt12bad_any_cast4whatEv', 'type': 'FUNC'}
3 {'is_defined': True, 'name': '_ZNKSt12experimental15fundamentals_v112bad_any_cast4whatEv', 'type': …
5 {'is_defined': True, 'name': '_ZNKSt16nested_exception14rethrow_nestedEv', 'type': 'FUNC'}
6 {'is_defined': True, 'name': '_ZNKSt18bad_variant_access4whatEv', 'type': 'FUNC'}
7 {'is_defined': True, 'name': '_ZNKSt19bad_optional_access4whatEv', 'type': 'FUNC'}
8 {'is_defined': True, 'name': '_ZNKSt3__110__time_put8__do_putEPcRS1_PK2tmcc', 'type': 'FUNC'}
9 {'is_defined': True, 'name': '_ZNKSt3__110__time_put8__do_putEPwRS1_PK2tmcc', 'type': 'FUNC'}
10 {'is_defined': True, 'name': '_ZNKSt3__110error_code7messageEv', 'type': 'FUNC'}
11 {'is_defined': True, 'name': '_ZNKSt3__110moneypunctIcLb0EE11do_groupingEv', 'type': 'FUNC'}
12 {'is_defined': True, 'name': '_ZNKSt3__110moneypunctIcLb0EE13do_neg_formatEv', 'type': 'FUNC'}
[all …]
Dx86_64-apple-darwin16.abilist2 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt10bad_typeid4whatEv'}
4 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt11logic_error4whatEv'}
5 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt12bad_any_cast4whatEv'}
6 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt12experimental15fundamentals_v112bad_any_cast4…
8 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt13bad_exception4whatEv'}
10 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt13runtime_error4whatEv'}
12 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt16bad_array_length4whatEv'}
13 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt16nested_exception14rethrow_nestedEv'}
14 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt18bad_variant_access4whatEv'}
15 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt19bad_optional_access4whatEv'}
[all …]
/external/libcxx/lib/abi/4.0/
Dx86_64-unknown-linux-gnu.abilist2 {'name': '_ZNKSt12bad_any_cast4whatEv', 'is_defined': True, 'type': 'FUNC'}
3 {'name': '_ZNKSt12experimental15fundamentals_v112bad_any_cast4whatEv', 'is_defined': True, 'type': …
5 {'name': '_ZNKSt16nested_exception14rethrow_nestedEv', 'is_defined': True, 'type': 'FUNC'}
6 {'name': '_ZNKSt18bad_variant_access4whatEv', 'is_defined': True, 'type': 'FUNC'}
7 {'name': '_ZNKSt19bad_optional_access4whatEv', 'is_defined': True, 'type': 'FUNC'}
8 {'name': '_ZNKSt3__110__time_put8__do_putEPcRS1_PK2tmcc', 'is_defined': True, 'type': 'FUNC'}
9 {'name': '_ZNKSt3__110__time_put8__do_putEPwRS1_PK2tmcc', 'is_defined': True, 'type': 'FUNC'}
10 {'name': '_ZNKSt3__110error_code7messageEv', 'is_defined': True, 'type': 'FUNC'}
11 {'name': '_ZNKSt3__110moneypunctIcLb0EE11do_groupingEv', 'is_defined': True, 'type': 'FUNC'}
12 {'name': '_ZNKSt3__110moneypunctIcLb0EE13do_neg_formatEv', 'is_defined': True, 'type': 'FUNC'}
[all …]
Dx86_64-apple-darwin16.abilist2 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt10bad_typeid4whatEv'}
4 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt11logic_error4whatEv'}
5 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt12bad_any_cast4whatEv'}
6 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt12experimental15fundamentals_v112bad_any_cast4…
8 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt13bad_exception4whatEv'}
10 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt13runtime_error4whatEv'}
12 {'type': 'I', 'is_defined': True, 'name': '__ZNKSt16bad_array_length4whatEv'}
13 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt16nested_exception14rethrow_nestedEv'}
14 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt18bad_variant_access4whatEv'}
15 {'type': 'FUNC', 'is_defined': True, 'name': '__ZNKSt19bad_optional_access4whatEv'}
[all …]
/external/icu/icu4j/main/classes/core/.settings/
Dedu.umd.cs.findbugs.core.prefs4 detectorAppendingToAnObjectOutputStream=AppendingToAnObjectOutputStream|true
5 detectorAtomicityProblem=AtomicityProblem|true
7 detectorBadResultSetAccess=BadResultSetAccess|true
8 detectorBadSyntaxForRegularExpression=BadSyntaxForRegularExpression|true
9 detectorBadUseOfReturnValue=BadUseOfReturnValue|true
10 detectorBadlyOverriddenAdapter=BadlyOverriddenAdapter|true
11 detectorBooleanReturnNull=BooleanReturnNull|true
14 detectorCheckImmutableAnnotation=CheckImmutableAnnotation|true
15 detectorCheckTypeQualifiers=CheckTypeQualifiers|true
16 detectorCloneIdiom=CloneIdiom|true
[all …]
/external/icu/icu4j/main/classes/translit/.settings/
Dedu.umd.cs.findbugs.core.prefs4 detectorAppendingToAnObjectOutputStream=AppendingToAnObjectOutputStream|true
5 detectorAtomicityProblem=AtomicityProblem|true
7 detectorBadResultSetAccess=BadResultSetAccess|true
8 detectorBadSyntaxForRegularExpression=BadSyntaxForRegularExpression|true
9 detectorBadUseOfReturnValue=BadUseOfReturnValue|true
10 detectorBadlyOverriddenAdapter=BadlyOverriddenAdapter|true
11 detectorBooleanReturnNull=BooleanReturnNull|true
14 detectorCheckImmutableAnnotation=CheckImmutableAnnotation|true
15 detectorCheckTypeQualifiers=CheckTypeQualifiers|true
16 detectorCloneIdiom=CloneIdiom|true
[all …]
/external/icu/icu4j/main/classes/collate/.settings/
Dedu.umd.cs.findbugs.core.prefs4 detectorAppendingToAnObjectOutputStream=AppendingToAnObjectOutputStream|true
5 detectorAtomicityProblem=AtomicityProblem|true
7 detectorBadResultSetAccess=BadResultSetAccess|true
8 detectorBadSyntaxForRegularExpression=BadSyntaxForRegularExpression|true
9 detectorBadUseOfReturnValue=BadUseOfReturnValue|true
10 detectorBadlyOverriddenAdapter=BadlyOverriddenAdapter|true
11 detectorBooleanReturnNull=BooleanReturnNull|true
14 detectorCheckImmutableAnnotation=CheckImmutableAnnotation|true
15 detectorCheckTypeQualifiers=CheckTypeQualifiers|true
16 detectorCloneIdiom=CloneIdiom|true
[all …]
/external/swiftshader/src/D3D9/
DCapabilities.cpp21 bool Capabilities::Surface::RenderTarget::NULL_ = true;
23 bool Capabilities::Surface::RenderTarget::R5G6B5 = true;
24 bool Capabilities::Surface::RenderTarget::X1R5G5B5 = true;
25 bool Capabilities::Surface::RenderTarget::A1R5G5B5 = true;
26 bool Capabilities::Surface::RenderTarget::A4R4G4B4 = true;
29 bool Capabilities::Surface::RenderTarget::X4R4G4B4 = true;
30 bool Capabilities::Surface::RenderTarget::A8R8G8B8 = true;
31 bool Capabilities::Surface::RenderTarget::X8R8G8B8 = true;
32 bool Capabilities::Surface::RenderTarget::A8B8G8R8 = true;
33 bool Capabilities::Surface::RenderTarget::X8B8G8R8 = true;
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-operand-rn-in-it-block-t32.cc78 // True if we need to generate an IT instruction for this test to be valid.
96 {{{eq, r0, r0}, true, eq, "eq r0 r0", "eq_r0_r0"},
97 {{eq, r0, r1}, true, eq, "eq r0 r1", "eq_r0_r1"},
98 {{eq, r0, r2}, true, eq, "eq r0 r2", "eq_r0_r2"},
99 {{eq, r0, r3}, true, eq, "eq r0 r3", "eq_r0_r3"},
100 {{eq, r0, r4}, true, eq, "eq r0 r4", "eq_r0_r4"},
101 {{eq, r0, r5}, true, eq, "eq r0 r5", "eq_r0_r5"},
102 {{eq, r0, r6}, true, eq, "eq r0 r6", "eq_r0_r6"},
103 {{eq, r0, r7}, true, eq, "eq r0 r7", "eq_r0_r7"},
104 {{eq, r0, r8}, true, eq, "eq r0 r8", "eq_r0_r8"},
[all …]
Dtest-assembler-cond-rdlow-operand-imm8-in-it-block-t32.cc78 // True if we need to generate an IT instruction for this test to be valid.
95 const TestData kTests[] = {{{vc, r1, 111}, true, vc, "vc r1 111", "vc_r1_111"},
96 {{ne, r1, 134}, true, ne, "ne r1 134", "ne_r1_134"},
97 {{ne, r5, 21}, true, ne, "ne r5 21", "ne_r5_21"},
98 {{cs, r6, 221}, true, cs, "cs r6 221", "cs_r6_221"},
99 {{cs, r3, 100}, true, cs, "cs r3 100", "cs_r3_100"},
100 {{le, r2, 209}, true, le, "le r2 209", "le_r2_209"},
101 {{ls, r7, 8}, true, ls, "ls r7 8", "ls_r7_8"},
102 {{cs, r7, 201}, true, cs, "cs r7 201", "cs_r7_201"},
103 {{ne, r3, 112}, true, ne, "ne r3 112", "ne_r3_112"},
[all …]
Dtest-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc78 // True if we need to generate an IT instruction for this test to be valid.
95 const TestData kTests[] = {{{eq, r0, r0}, true, eq, "eq r0 r0", "eq_r0_r0"},
96 {{eq, r0, r1}, true, eq, "eq r0 r1", "eq_r0_r1"},
97 {{eq, r0, r2}, true, eq, "eq r0 r2", "eq_r0_r2"},
98 {{eq, r0, r3}, true, eq, "eq r0 r3", "eq_r0_r3"},
99 {{eq, r0, r4}, true, eq, "eq r0 r4", "eq_r0_r4"},
100 {{eq, r0, r5}, true, eq, "eq r0 r5", "eq_r0_r5"},
101 {{eq, r0, r6}, true, eq, "eq r0 r6", "eq_r0_r6"},
102 {{eq, r0, r7}, true, eq, "eq r0 r7", "eq_r0_r7"},
103 {{eq, r1, r0}, true, eq, "eq r1 r0", "eq_r1_r0"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc77 // True if we need to generate an IT instruction for this test to be valid.
95 {{{eq, r0, r0, 0}, true, eq, "eq r0 r0 0", "eq_r0_r0_0"},
96 {{eq, r0, r1, 0}, true, eq, "eq r0 r1 0", "eq_r0_r1_0"},
97 {{eq, r0, r2, 0}, true, eq, "eq r0 r2 0", "eq_r0_r2_0"},
98 {{eq, r0, r3, 0}, true, eq, "eq r0 r3 0", "eq_r0_r3_0"},
99 {{eq, r0, r4, 0}, true, eq, "eq r0 r4 0", "eq_r0_r4_0"},
100 {{eq, r0, r5, 0}, true, eq, "eq r0 r5 0", "eq_r0_r5_0"},
101 {{eq, r0, r6, 0}, true, eq, "eq r0 r6 0", "eq_r0_r6_0"},
102 {{eq, r0, r7, 0}, true, eq, "eq r0 r7 0", "eq_r0_r7_0"},
103 {{eq, r1, r0, 0}, true, eq, "eq r1 r0 0", "eq_r1_r0_0"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc77 // True if we need to generate an IT instruction for this test to be valid.
95 {{{eq, r0, r0, r0}, true, eq, "eq r0 r0 r0", "eq_r0_r0_r0"},
96 {{eq, r0, r1, r0}, true, eq, "eq r0 r1 r0", "eq_r0_r1_r0"},
97 {{eq, r0, r2, r0}, true, eq, "eq r0 r2 r0", "eq_r0_r2_r0"},
98 {{eq, r0, r3, r0}, true, eq, "eq r0 r3 r0", "eq_r0_r3_r0"},
99 {{eq, r0, r4, r0}, true, eq, "eq r0 r4 r0", "eq_r0_r4_r0"},
100 {{eq, r0, r5, r0}, true, eq, "eq r0 r5 r0", "eq_r0_r5_r0"},
101 {{eq, r0, r6, r0}, true, eq, "eq r0 r6 r0", "eq_r0_r6_r0"},
102 {{eq, r0, r7, r0}, true, eq, "eq r0 r7 r0", "eq_r0_r7_r0"},
103 {{eq, r1, r0, r1}, true, eq, "eq r1 r0 r1", "eq_r1_r0_r1"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc79 // True if we need to generate an IT instruction for this test to be valid.
97 {{{pl, r0, r0, 7}, true, pl, "pl r0 r0 7", "pl_r0_r0_7"},
98 {{cs, r0, r2, 5}, true, cs, "cs r0 r2 5", "cs_r0_r2_5"},
99 {{ls, r1, r6, 0}, true, ls, "ls r1 r6 0", "ls_r1_r6_0"},
100 {{cc, r5, r1, 6}, true, cc, "cc r5 r1 6", "cc_r5_r1_6"},
101 {{cs, r5, r2, 0}, true, cs, "cs r5 r2 0", "cs_r5_r2_0"},
102 {{vs, r5, r6, 7}, true, vs, "vs r5 r6 7", "vs_r5_r6_7"},
103 {{ls, r2, r0, 5}, true, ls, "ls r2 r0 5", "ls_r2_r0_5"},
104 {{eq, r3, r4, 5}, true, eq, "eq r3 r4 5", "eq_r3_r4_5"},
105 {{lt, r4, r5, 7}, true, lt, "lt r4 r5 7", "lt_r4_r5_7"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc79 // True if we need to generate an IT instruction for this test to be valid.
97 {{{mi, r3, r3, 90}, true, mi, "mi r3 r3 90", "mi_r3_r3_90"},
98 {{vc, r6, r6, 138}, true, vc, "vc r6 r6 138", "vc_r6_r6_138"},
99 {{cc, r5, r5, 72}, true, cc, "cc r5 r5 72", "cc_r5_r5_72"},
100 {{ge, r6, r6, 181}, true, ge, "ge r6 r6 181", "ge_r6_r6_181"},
101 {{cc, r1, r1, 143}, true, cc, "cc r1 r1 143", "cc_r1_r1_143"},
102 {{vc, r5, r5, 114}, true, vc, "vc r5 r5 114", "vc_r5_r5_114"},
103 {{ge, r4, r4, 195}, true, ge, "ge r4 r4 195", "ge_r4_r4_195"},
104 {{lt, r0, r0, 203}, true, lt, "lt r0 r0 203", "lt_r0_r0_203"},
105 {{hi, r1, r1, 98}, true, hi, "hi r1 r1 98", "hi_r1_r1_98"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc78 // True if we need to generate an IT instruction for this test to be valid.
96 {{{ge, r1, r1, LSL, r6}, true, ge, "ge r1 r1 LSL r6", "ge_r1_r1_LSL_r6"},
97 {{cs, r7, r7, LSL, r2}, true, cs, "cs r7 r7 LSL r2", "cs_r7_r7_LSL_r2"},
98 {{gt, r1, r1, LSL, r0}, true, gt, "gt r1 r1 LSL r0", "gt_r1_r1_LSL_r0"},
99 {{pl, r3, r3, ROR, r3}, true, pl, "pl r3 r3 ROR r3", "pl_r3_r3_ROR_r3"},
100 {{vc, r4, r4, ROR, r1}, true, vc, "vc r4 r4 ROR r1", "vc_r4_r4_ROR_r1"},
101 {{vs, r2, r2, LSL, r0}, true, vs, "vs r2 r2 LSL r0", "vs_r2_r2_LSL_r0"},
102 {{vc, r4, r4, LSR, r4}, true, vc, "vc r4 r4 LSR r4", "vc_r4_r4_LSR_r4"},
103 {{le, r6, r6, ASR, r6}, true, le, "le r6 r6 ASR r6", "le_r6_r6_ASR_r6"},
104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to31-in-it-block-t32.cc78 // True if we need to generate an IT instruction for this test to be valid.
96 {{{hi, r2, r4, LSL, 10}, true, hi, "hi r2 r4 LSL 10", "hi_r2_r4_LSL_10"},
97 {{cs, r6, r2, LSL, 8}, true, cs, "cs r6 r2 LSL 8", "cs_r6_r2_LSL_8"},
98 {{lt, r5, r3, LSL, 21}, true, lt, "lt r5 r3 LSL 21", "lt_r5_r3_LSL_21"},
99 {{ge, r5, r0, LSL, 3}, true, ge, "ge r5 r0 LSL 3", "ge_r5_r0_LSL_3"},
100 {{mi, r4, r1, LSL, 4}, true, mi, "mi r4 r1 LSL 4", "mi_r4_r1_LSL_4"},
101 {{ge, r6, r6, LSL, 28}, true, ge, "ge r6 r6 LSL 28", "ge_r6_r6_LSL_28"},
102 {{lt, r4, r2, LSL, 31}, true, lt, "lt r4 r2 LSL 31", "lt_r4_r2_LSL_31"},
103 {{eq, r0, r3, LSL, 17}, true, eq, "eq r0 r3 LSL 17", "eq_r0_r3_LSL_17"},
104 {{vc, r2, r2, LSL, 22}, true, vc, "vc r2 r2 LSL 22", "vc_r2_r2_LSL_22"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-rd-is-rn-in-it-block-t32.cc77 // True if we need to generate an IT instruction for this test to be valid.
95 {{{pl, r13, r13, r1}, true, pl, "pl r13 r13 r1", "pl_r13_r13_r1"},
96 {{mi, r11, r11, r4}, true, mi, "mi r11 r11 r4", "mi_r11_r11_r4"},
97 {{vs, r4, r4, r2}, true, vs, "vs r4 r4 r2", "vs_r4_r4_r2"},
98 {{ls, r7, r7, r6}, true, ls, "ls r7 r7 r6", "ls_r7_r7_r6"},
99 {{le, r4, r4, r2}, true, le, "le r4 r4 r2", "le_r4_r4_r2"},
100 {{vc, r11, r11, r0}, true, vc, "vc r11 r11 r0", "vc_r11_r11_r0"},
101 {{le, r6, r6, r11}, true, le, "le r6 r6 r11", "le_r6_r6_r11"},
102 {{eq, r4, r4, r9}, true, eq, "eq r4 r4 r9", "eq_r4_r4_r9"},
103 {{hi, r12, r12, r2}, true, hi, "hi r12 r12 r2", "hi_r12_r12_r2"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc87 // True if we need to generate an IT instruction for this test to be valid.
105 {{{gt, r3, r3, r0}, true, gt, "gt r3 r3 r0", "gt_r3_r3_r0"},
106 {{ge, r6, r6, r1}, true, ge, "ge r6 r6 r1", "ge_r6_r6_r1"},
107 {{gt, r7, r7, r1}, true, gt, "gt r7 r7 r1", "gt_r7_r7_r1"},
108 {{gt, r2, r2, r0}, true, gt, "gt r2 r2 r0", "gt_r2_r2_r0"},
109 {{eq, r5, r5, r2}, true, eq, "eq r5 r5 r2", "eq_r5_r5_r2"},
110 {{gt, r0, r0, r0}, true, gt, "gt r0 r0 r0", "gt_r0_r0_r0"},
111 {{lt, r0, r0, r4}, true, lt, "lt r0 r0 r4", "lt_r0_r0_r4"},
112 {{hi, r6, r6, r3}, true, hi, "hi r6 r6 r3", "hi_r6_r6_r3"},
113 {{ge, r7, r7, r6}, true, ge, "ge r7 r7 r6", "ge_r7_r7_r6"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc79 // True if we need to generate an IT instruction for this test to be valid.
97 {{{cs, r7, r1, r5}, true, cs, "cs r7 r1 r5", "cs_r7_r1_r5"},
98 {{gt, r3, r1, r0}, true, gt, "gt r3 r1 r0", "gt_r3_r1_r0"},
99 {{ls, r4, r3, r6}, true, ls, "ls r4 r3 r6", "ls_r4_r3_r6"},
100 {{pl, r5, r3, r4}, true, pl, "pl r5 r3 r4", "pl_r5_r3_r4"},
101 {{hi, r1, r0, r0}, true, hi, "hi r1 r0 r0", "hi_r1_r0_r0"},
102 {{ls, r1, r2, r3}, true, ls, "ls r1 r2 r3", "ls_r1_r2_r3"},
103 {{vc, r4, r3, r4}, true, vc, "vc r4 r3 r4", "vc_r4_r3_r4"},
104 {{ne, r1, r7, r0}, true, ne, "ne r1 r7 r0", "ne_r1_r7_r0"},
105 {{ls, r3, r4, r0}, true, ls, "ls r3 r4 r0", "ls_r3_r4_r0"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc78 // True if we need to generate an IT instruction for this test to be valid.
96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
97 {{gt, r4, r6, LSR, 32}, true, gt, "gt r4 r6 LSR 32", "gt_r4_r6_LSR_32"},
98 {{hi, r6, r7, LSR, 29}, true, hi, "hi r6 r7 LSR 29", "hi_r6_r7_LSR_29"},
99 {{mi, r7, r1, LSR, 10}, true, mi, "mi r7 r1 LSR 10", "mi_r7_r1_LSR_10"},
100 {{ls, r7, r6, LSR, 14}, true, ls, "ls r7 r6 LSR 14", "ls_r7_r6_LSR_14"},
101 {{eq, r7, r2, ASR, 14}, true, eq, "eq r7 r2 ASR 14", "eq_r7_r2_ASR_14"},
102 {{le, r3, r7, LSR, 2}, true, le, "le r3 r7 LSR 2", "le_r3_r7_LSR_2"},
103 {{mi, r2, r7, LSR, 32}, true, mi, "mi r2 r7 LSR 32", "mi_r2_r7_LSR_32"},
104 {{ge, r5, r0, ASR, 23}, true, ge, "ge r5 r0 ASR 23", "ge_r5_r0_ASR_23"},
[all …]
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_extensions.c43 ctx->Extensions.ARB_arrays_of_arrays = true; in intelInitExtensions()
44 ctx->Extensions.ARB_buffer_storage = true; in intelInitExtensions()
45 ctx->Extensions.ARB_clear_texture = true; in intelInitExtensions()
46 ctx->Extensions.ARB_clip_control = true; in intelInitExtensions()
47 ctx->Extensions.ARB_copy_image = true; in intelInitExtensions()
48 ctx->Extensions.ARB_depth_buffer_float = true; in intelInitExtensions()
49 ctx->Extensions.ARB_depth_clamp = true; in intelInitExtensions()
50 ctx->Extensions.ARB_depth_texture = true; in intelInitExtensions()
51 ctx->Extensions.ARB_draw_elements_base_vertex = true; in intelInitExtensions()
52 ctx->Extensions.ARB_draw_instanced = true; in intelInitExtensions()
[all …]
/external/swiftshader/src/D3D8/
DCapabilities.cpp22 bool Capabilities::Surface::RenderTarget::R5G6B5 = true;
23 bool Capabilities::Surface::RenderTarget::X1R5G5B5 = true;
24 bool Capabilities::Surface::RenderTarget::A1R5G5B5 = true;
25 bool Capabilities::Surface::RenderTarget::A4R4G4B4 = true;
28 bool Capabilities::Surface::RenderTarget::X4R4G4B4 = true;
29 bool Capabilities::Surface::RenderTarget::A8R8G8B8 = true;
30 bool Capabilities::Surface::RenderTarget::X8R8G8B8 = true;
31 bool Capabilities::Surface::RenderTarget::A8B8G8R8 = true;
32 bool Capabilities::Surface::RenderTarget::X8B8G8R8 = true;
33 bool Capabilities::Surface::RenderTarget::G16R16 = true;
[all …]
/external/jacoco/org.jacoco.core.test/src/org/jacoco/core/internal/flow/
DLabelFlowAnalyzerTest.java147 testInsn(NOP, true); in testInsn()
148 testInsn(ACONST_NULL, true); in testInsn()
149 testInsn(ICONST_M1, true); in testInsn()
150 testInsn(ICONST_0, true); in testInsn()
151 testInsn(ICONST_1, true); in testInsn()
152 testInsn(ICONST_2, true); in testInsn()
153 testInsn(ICONST_3, true); in testInsn()
154 testInsn(ICONST_4, true); in testInsn()
155 testInsn(ICONST_5, true); in testInsn()
156 testInsn(LCONST_0, true); in testInsn()
[all …]
/external/python/cpython3/Lib/test/
Dtest_bool.py24 print(False, True, file=fo)
27 self.assertEqual(fo.read(), 'False True\n')
34 self.assertEqual(repr(True), 'True')
36 self.assertEqual(eval(repr(True)), True)
40 self.assertEqual(str(True), 'True')
45 self.assertEqual(int(True), 1)
46 self.assertIsNot(int(True), True)
51 self.assertEqual(float(True), 1.0)
52 self.assertIsNot(float(True), True)
61 self.assertEqual(+True, 1)
[all …]

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