1 /*
2 * Copyright (c) 2012-2015 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef H_ETNA_INTERNAL
25 #define H_ETNA_INTERNAL
26
27 #include <assert.h>
28 #include <stdbool.h>
29 #include <stdint.h>
30
31 #include "hw/state.xml.h"
32 #include "hw/state_3d.xml.h"
33
34 #include <etnaviv_drmif.h>
35
36 #define ETNA_NUM_INPUTS (16)
37 #define ETNA_NUM_VARYINGS 8
38 #define ETNA_NUM_LOD (14)
39 #define ETNA_NUM_LAYERS (6)
40 #define ETNA_MAX_UNIFORMS (256)
41 #define ETNA_MAX_PIXELPIPES 2
42
43 /* All RS operations must have width%16 = 0 */
44 #define ETNA_RS_WIDTH_MASK (16 - 1)
45 /* RS tiled operations must have height%4 = 0 */
46 #define ETNA_RS_HEIGHT_MASK (3)
47 /* PE render targets must be aligned to 64 bytes */
48 #define ETNA_PE_ALIGNMENT (64)
49
50 /* These demarcate the margin (fixp16) between the computed sizes and the
51 value sent to the chip. These have been set to the numbers used by the
52 Vivante driver on gc2000. They used to be -1 for scissor right and bottom. I
53 am not sure whether older hardware was relying on these or they were just a
54 guess. But if so, these need to be moved to the _specs structure.
55 */
56 #define ETNA_SE_SCISSOR_MARGIN_RIGHT (0x1119)
57 #define ETNA_SE_SCISSOR_MARGIN_BOTTOM (0x1111)
58 #define ETNA_SE_CLIP_MARGIN_RIGHT (0xffff)
59 #define ETNA_SE_CLIP_MARGIN_BOTTOM (0xffff)
60
61 /* GPU chip 3D specs */
62 struct etna_specs {
63 /* supports SUPERTILE (64x64) tiling? */
64 unsigned can_supertile : 1;
65 /* needs z=(z+w)/2, for older GCxxx */
66 unsigned vs_need_z_div : 1;
67 /* supports trigonometric instructions */
68 unsigned has_sin_cos_sqrt : 1;
69 /* has SIGN/FLOOR/CEIL instructions */
70 unsigned has_sign_floor_ceil : 1;
71 /* can use VS_RANGE, PS_RANGE registers*/
72 unsigned has_shader_range_registers : 1;
73 /* has the new sin/cos functions */
74 unsigned has_new_sin_cos : 1;
75 /* can use any kind of wrapping mode on npot textures */
76 unsigned npot_tex_any_wrap;
77 /* number of bits per TS tile */
78 unsigned bits_per_tile;
79 /* clear value for TS (dependent on bits_per_tile) */
80 uint32_t ts_clear_value;
81 /* base of vertex texture units */
82 unsigned vertex_sampler_offset;
83 /* number of fragment sampler units */
84 unsigned fragment_sampler_count;
85 /* number of vertex sampler units */
86 unsigned vertex_sampler_count;
87 /* size of vertex shader output buffer */
88 unsigned vertex_output_buffer_size;
89 /* maximum number of vertex element configurations */
90 unsigned vertex_max_elements;
91 /* size of a cached vertex (?) */
92 unsigned vertex_cache_size;
93 /* number of shader cores */
94 unsigned shader_core_count;
95 /* number of vertex streams */
96 unsigned stream_count;
97 /* vertex shader memory address*/
98 uint32_t vs_offset;
99 /* pixel shader memory address*/
100 uint32_t ps_offset;
101 /* vertex/fragment shader max instructions */
102 uint32_t max_instructions;
103 /* maximum number of varyings */
104 unsigned max_varyings;
105 /* maximum number of registers */
106 unsigned max_registers;
107 /* maximum vertex uniforms */
108 unsigned max_vs_uniforms;
109 /* maximum pixel uniforms */
110 unsigned max_ps_uniforms;
111 /* maximum texture size */
112 unsigned max_texture_size;
113 /* maximum texture size */
114 unsigned max_rendertarget_size;
115 /* available pixel pipes */
116 unsigned pixel_pipes;
117 /* number of constants */
118 unsigned num_constants;
119 };
120
121 /* Compiled Gallium state. All the different compiled state atoms are woven
122 * together and uploaded only when it is necessary to synchronize the state,
123 * for example before rendering. */
124
125 /* Compiled pipe_blend_color */
126 struct compiled_blend_color {
127 uint32_t PE_ALPHA_BLEND_COLOR;
128 };
129
130 /* Compiled pipe_stencil_ref */
131 struct compiled_stencil_ref {
132 uint32_t PE_STENCIL_CONFIG;
133 uint32_t PE_STENCIL_CONFIG_EXT;
134 };
135
136 /* Compiled pipe_scissor_state */
137 struct compiled_scissor_state {
138 uint32_t SE_SCISSOR_LEFT;
139 uint32_t SE_SCISSOR_TOP;
140 uint32_t SE_SCISSOR_RIGHT;
141 uint32_t SE_SCISSOR_BOTTOM;
142 uint32_t SE_CLIP_RIGHT;
143 uint32_t SE_CLIP_BOTTOM;
144 };
145
146 /* Compiled pipe_viewport_state */
147 struct compiled_viewport_state {
148 uint32_t PA_VIEWPORT_SCALE_X;
149 uint32_t PA_VIEWPORT_SCALE_Y;
150 uint32_t PA_VIEWPORT_SCALE_Z;
151 uint32_t PA_VIEWPORT_OFFSET_X;
152 uint32_t PA_VIEWPORT_OFFSET_Y;
153 uint32_t PA_VIEWPORT_OFFSET_Z;
154 uint32_t SE_SCISSOR_LEFT;
155 uint32_t SE_SCISSOR_TOP;
156 uint32_t SE_SCISSOR_RIGHT;
157 uint32_t SE_SCISSOR_BOTTOM;
158 uint32_t SE_CLIP_RIGHT;
159 uint32_t SE_CLIP_BOTTOM;
160 uint32_t PE_DEPTH_NEAR;
161 uint32_t PE_DEPTH_FAR;
162 };
163
164 /* Compiled pipe_framebuffer_state */
165 struct compiled_framebuffer_state {
166 struct pipe_surface *cbuf, *zsbuf; /* keep reference to surfaces */
167 uint32_t GL_MULTI_SAMPLE_CONFIG;
168 uint32_t PE_COLOR_FORMAT;
169 uint32_t PE_DEPTH_CONFIG;
170 struct etna_reloc PE_DEPTH_ADDR;
171 struct etna_reloc PE_PIPE_DEPTH_ADDR[ETNA_MAX_PIXELPIPES];
172 uint32_t PE_DEPTH_STRIDE;
173 uint32_t PE_HDEPTH_CONTROL;
174 uint32_t PE_DEPTH_NORMALIZE;
175 struct etna_reloc PE_COLOR_ADDR;
176 struct etna_reloc PE_PIPE_COLOR_ADDR[ETNA_MAX_PIXELPIPES];
177 uint32_t PE_COLOR_STRIDE;
178 uint32_t SE_SCISSOR_LEFT;
179 uint32_t SE_SCISSOR_TOP;
180 uint32_t SE_SCISSOR_RIGHT;
181 uint32_t SE_SCISSOR_BOTTOM;
182 uint32_t SE_CLIP_RIGHT;
183 uint32_t SE_CLIP_BOTTOM;
184 uint32_t RA_MULTISAMPLE_UNK00E04;
185 uint32_t RA_MULTISAMPLE_UNK00E10[VIVS_RA_MULTISAMPLE_UNK00E10__LEN];
186 uint32_t RA_CENTROID_TABLE[VIVS_RA_CENTROID_TABLE__LEN];
187 uint32_t TS_MEM_CONFIG;
188 uint32_t TS_DEPTH_CLEAR_VALUE;
189 struct etna_reloc TS_DEPTH_STATUS_BASE;
190 struct etna_reloc TS_DEPTH_SURFACE_BASE;
191 uint32_t TS_COLOR_CLEAR_VALUE;
192 struct etna_reloc TS_COLOR_STATUS_BASE;
193 struct etna_reloc TS_COLOR_SURFACE_BASE;
194 bool msaa_mode; /* adds input (and possible temp) to PS */
195 };
196
197 /* Compiled context->create_vertex_elements_state */
198 struct compiled_vertex_elements_state {
199 unsigned num_elements;
200 uint32_t FE_VERTEX_ELEMENT_CONFIG[VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN];
201 };
202
203 /* Compiled context->set_vertex_buffer result */
204 struct compiled_set_vertex_buffer {
205 uint32_t FE_VERTEX_STREAM_CONTROL;
206 struct etna_reloc FE_VERTEX_STREAM_BASE_ADDR;
207 };
208
209 /* Compiled linked VS+PS shader state */
210 struct compiled_shader_state {
211 uint32_t RA_CONTROL;
212 uint32_t PA_ATTRIBUTE_ELEMENT_COUNT;
213 uint32_t PA_CONFIG;
214 uint32_t PA_SHADER_ATTRIBUTES[VIVS_PA_SHADER_ATTRIBUTES__LEN];
215 uint32_t VS_END_PC;
216 uint32_t VS_OUTPUT_COUNT; /* number of outputs if point size per vertex disabled */
217 uint32_t VS_OUTPUT_COUNT_PSIZE; /* number of outputs of point size per vertex enabled */
218 uint32_t VS_INPUT_COUNT;
219 uint32_t VS_TEMP_REGISTER_CONTROL;
220 uint32_t VS_OUTPUT[4];
221 uint32_t VS_INPUT[4];
222 uint32_t VS_LOAD_BALANCING;
223 uint32_t VS_START_PC;
224 uint32_t PS_END_PC;
225 uint32_t PS_OUTPUT_REG;
226 uint32_t PS_INPUT_COUNT;
227 uint32_t PS_INPUT_COUNT_MSAA; /* Adds an input */
228 uint32_t PS_TEMP_REGISTER_CONTROL;
229 uint32_t PS_TEMP_REGISTER_CONTROL_MSAA; /* Adds a temporary if needed to make space for extra input */
230 uint32_t PS_CONTROL;
231 uint32_t PS_START_PC;
232 uint32_t GL_VARYING_TOTAL_COMPONENTS;
233 uint32_t GL_VARYING_NUM_COMPONENTS;
234 uint32_t GL_VARYING_COMPONENT_USE[2];
235 unsigned vs_inst_mem_size;
236 unsigned vs_uniforms_size;
237 unsigned ps_inst_mem_size;
238 unsigned ps_uniforms_size;
239 uint32_t *VS_INST_MEM;
240 uint32_t VS_UNIFORMS[ETNA_MAX_UNIFORMS * 4];
241 uint32_t *PS_INST_MEM;
242 uint32_t PS_UNIFORMS[ETNA_MAX_UNIFORMS * 4];
243 };
244
245 /* state of some 3d and common registers relevant to etna driver */
246 struct etna_3d_state {
247 unsigned vs_uniforms_size;
248 unsigned ps_uniforms_size;
249
250 uint32_t /*01008*/ PS_INPUT_COUNT;
251 uint32_t /*0100C*/ PS_TEMP_REGISTER_CONTROL;
252 uint32_t /*03818*/ GL_MULTI_SAMPLE_CONFIG;
253 uint32_t /*05000*/ VS_UNIFORMS[VIVS_VS_UNIFORMS__LEN];
254 uint32_t /*07000*/ PS_UNIFORMS[VIVS_PS_UNIFORMS__LEN];
255 };
256
257 /* Helpers to assist creating and setting bitarrays (eg, for varyings).
258 * field_size must be a power of two, and <= 32. */
259 #define DEFINE_ETNA_BITARRAY(name, num, field_size) \
260 uint32_t name[(num) * (field_size) / 32]
261
262 static inline void
etna_bitarray_set(uint32_t * array,size_t array_size,size_t field_size,size_t index,uint32_t value)263 etna_bitarray_set(uint32_t *array, size_t array_size, size_t field_size,
264 size_t index, uint32_t value)
265 {
266 size_t shift = (index * field_size) % 32;
267 size_t offset = (index * field_size) / 32;
268
269 assert(index < array_size * 32 / field_size);
270 assert(value < 1 << field_size);
271
272 array[offset] |= value << shift;
273 }
274
275 #define etna_bitarray_set(array, field_size, index, value) \
276 etna_bitarray_set((array), ARRAY_SIZE(array), field_size, index, value)
277
278 #endif
279