1 // Copyright 2014 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 7 8 namespace v8 { 9 namespace internal { 10 namespace compiler { 11 12 // MIPS-specific opcodes that specify which assembly sequence to emit. 13 // Most opcodes specify a single instruction. 14 #define TARGET_ARCH_OPCODE_LIST(V) \ 15 V(MipsAdd) \ 16 V(MipsAddOvf) \ 17 V(MipsSub) \ 18 V(MipsSubOvf) \ 19 V(MipsMul) \ 20 V(MipsMulOvf) \ 21 V(MipsMulHigh) \ 22 V(MipsMulHighU) \ 23 V(MipsDiv) \ 24 V(MipsDivU) \ 25 V(MipsMod) \ 26 V(MipsModU) \ 27 V(MipsAnd) \ 28 V(MipsOr) \ 29 V(MipsNor) \ 30 V(MipsXor) \ 31 V(MipsClz) \ 32 V(MipsCtz) \ 33 V(MipsPopcnt) \ 34 V(MipsLsa) \ 35 V(MipsShl) \ 36 V(MipsShr) \ 37 V(MipsSar) \ 38 V(MipsShlPair) \ 39 V(MipsShrPair) \ 40 V(MipsSarPair) \ 41 V(MipsExt) \ 42 V(MipsIns) \ 43 V(MipsRor) \ 44 V(MipsMov) \ 45 V(MipsTst) \ 46 V(MipsCmp) \ 47 V(MipsCmpS) \ 48 V(MipsAddS) \ 49 V(MipsSubS) \ 50 V(MipsMulS) \ 51 V(MipsDivS) \ 52 V(MipsModS) \ 53 V(MipsAbsS) \ 54 V(MipsSqrtS) \ 55 V(MipsMaxS) \ 56 V(MipsMinS) \ 57 V(MipsCmpD) \ 58 V(MipsAddD) \ 59 V(MipsSubD) \ 60 V(MipsMulD) \ 61 V(MipsDivD) \ 62 V(MipsModD) \ 63 V(MipsAbsD) \ 64 V(MipsSqrtD) \ 65 V(MipsMaxD) \ 66 V(MipsMinD) \ 67 V(MipsNegS) \ 68 V(MipsNegD) \ 69 V(MipsAddPair) \ 70 V(MipsSubPair) \ 71 V(MipsMulPair) \ 72 V(MipsMaddS) \ 73 V(MipsMaddD) \ 74 V(MipsMsubS) \ 75 V(MipsMsubD) \ 76 V(MipsFloat32RoundDown) \ 77 V(MipsFloat32RoundTruncate) \ 78 V(MipsFloat32RoundUp) \ 79 V(MipsFloat32RoundTiesEven) \ 80 V(MipsFloat64RoundDown) \ 81 V(MipsFloat64RoundTruncate) \ 82 V(MipsFloat64RoundUp) \ 83 V(MipsFloat64RoundTiesEven) \ 84 V(MipsCvtSD) \ 85 V(MipsCvtDS) \ 86 V(MipsTruncWD) \ 87 V(MipsRoundWD) \ 88 V(MipsFloorWD) \ 89 V(MipsCeilWD) \ 90 V(MipsTruncWS) \ 91 V(MipsRoundWS) \ 92 V(MipsFloorWS) \ 93 V(MipsCeilWS) \ 94 V(MipsTruncUwD) \ 95 V(MipsTruncUwS) \ 96 V(MipsCvtDW) \ 97 V(MipsCvtDUw) \ 98 V(MipsCvtSW) \ 99 V(MipsCvtSUw) \ 100 V(MipsLb) \ 101 V(MipsLbu) \ 102 V(MipsSb) \ 103 V(MipsLh) \ 104 V(MipsUlh) \ 105 V(MipsLhu) \ 106 V(MipsUlhu) \ 107 V(MipsSh) \ 108 V(MipsUsh) \ 109 V(MipsLw) \ 110 V(MipsUlw) \ 111 V(MipsSw) \ 112 V(MipsUsw) \ 113 V(MipsLwc1) \ 114 V(MipsUlwc1) \ 115 V(MipsSwc1) \ 116 V(MipsUswc1) \ 117 V(MipsLdc1) \ 118 V(MipsUldc1) \ 119 V(MipsSdc1) \ 120 V(MipsUsdc1) \ 121 V(MipsFloat64ExtractLowWord32) \ 122 V(MipsFloat64ExtractHighWord32) \ 123 V(MipsFloat64InsertLowWord32) \ 124 V(MipsFloat64InsertHighWord32) \ 125 V(MipsFloat64SilenceNaN) \ 126 V(MipsFloat32Max) \ 127 V(MipsFloat64Max) \ 128 V(MipsFloat32Min) \ 129 V(MipsFloat64Min) \ 130 V(MipsPush) \ 131 V(MipsStoreToStackSlot) \ 132 V(MipsByteSwap32) \ 133 V(MipsStackClaim) \ 134 V(MipsSeb) \ 135 V(MipsSeh) 136 137 // Addressing modes represent the "shape" of inputs to an instruction. 138 // Many instructions support multiple addressing modes. Addressing modes 139 // are encoded into the InstructionCode of the instruction and tell the 140 // code generator after register allocation which assembler method to call. 141 // 142 // We use the following local notation for addressing modes: 143 // 144 // R = register 145 // O = register or stack slot 146 // D = double register 147 // I = immediate (handle, external, int32) 148 // MRI = [register + immediate] 149 // MRR = [register + register] 150 // TODO(plind): Add the new r6 address modes. 151 #define TARGET_ADDRESSING_MODE_LIST(V) \ 152 V(MRI) /* [%r0 + K] */ \ 153 V(MRR) /* [%r0 + %r1] */ 154 155 156 } // namespace compiler 157 } // namespace internal 158 } // namespace v8 159 160 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ 161