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Searched refs:LR (Results 1 – 13 of 13) sorted by relevance

/art/disassembler/
Ddisassembler_arm64.cc41 LR = 30 enumerator
51 } else if (reg.GetCode() == LR) { in AppendRegisterNameToOutput()
/art/runtime/arch/arm/
Dregisters_arm.h48 LR = 14, enumerator
Dquick_method_frame_info_arm.h31 (1 << art::arm::LR);
104 POPCOUNT(ArmCalleeSaveCoreSpills(type) & (-(1 << LR))) * static_cast<size_t>(kArmPointerSize); in ArmCalleeSaveLrOffset()
Dquick_entrypoints_arm.S664 ldr r14, [r0, #56] @ (LR from gprs_ 56=4*14)
/art/runtime/arch/arm64/
Dquick_method_frame_info_arm64.h36 (1 << art::arm64::LR);
128 POPCOUNT(Arm64CalleeSaveCoreSpills(type) & (-(1 << LR))) * in Arm64CalleeSaveLrOffset()
Dregisters_arm64.h68 LR = X30, enumerator
/art/compiler/jni/quick/arm64/
Dcalling_convention_arm64.cc73 Arm64ManagedRegister::FromXRegister(LR),
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc97 uint32_t result = 1 << LR; in CalculateCoreCalleeSpillMask()
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc66 RegList core_spill_mask = 1 << LR; in BuildFrame()
126 RegList core_spill_mask = 1 << LR; in RemoveFrame()
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc631 EXPECT_TRUE(vixl::aarch64::lr.Is(Arm64Assembler::reg_x(LR))); in TEST()
/art/compiler/optimizing/
Dintrinsics_arm64.cc195 DCHECK_NE(tmp_.reg(), LR); in EmitNativeCode()
Dcode_generator_arm_vixl.cc2369 AddAllocatedRegister(Location::RegisterLocation(LR)); in CodeGeneratorARMVIXL()
2430 blocked_core_registers_[LR] = true; in SetupBlockedRegisters()
Dcode_generator_arm64.cc631 DCHECK_NE(ref_.reg(), LR); in GenerateReadBarrierMarkRuntimeCall()