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123

/art/compiler/utils/x86_64/
Dassembler_x86_64.cc134 void X86_64Assembler::movq(CpuRegister dst, const Immediate& imm) { in movq() argument
138 EmitRex64(dst); in movq()
140 EmitRegisterOperand(0, dst.LowBits()); in movq()
143 EmitRex64(dst); in movq()
144 EmitUint8(0xB8 + dst.LowBits()); in movq()
150 void X86_64Assembler::movl(CpuRegister dst, const Immediate& imm) { in movl() argument
153 EmitOptionalRex32(dst); in movl()
154 EmitUint8(0xB8 + dst.LowBits()); in movl()
159 void X86_64Assembler::movq(const Address& dst, const Immediate& imm) { in movq() argument
162 EmitRex64(dst); in movq()
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Dassembler_x86_64.h374 void movq(CpuRegister dst, const Immediate& src);
375 void movl(CpuRegister dst, const Immediate& src);
376 void movq(CpuRegister dst, CpuRegister src);
377 void movl(CpuRegister dst, CpuRegister src);
379 void movntl(const Address& dst, CpuRegister src);
380 void movntq(const Address& dst, CpuRegister src);
382 void movq(CpuRegister dst, const Address& src);
383 void movl(CpuRegister dst, const Address& src);
384 void movq(const Address& dst, CpuRegister src);
385 void movq(const Address& dst, const Immediate& imm);
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/art/compiler/utils/x86/
Dassembler_x86.h330 void movl(Register dst, const Immediate& src);
331 void movl(Register dst, Register src);
333 void movl(Register dst, const Address& src);
334 void movl(const Address& dst, Register src);
335 void movl(const Address& dst, const Immediate& imm);
336 void movl(const Address& dst, Label* lbl);
338 void movntl(const Address& dst, Register src);
340 void bswapl(Register dst);
342 void bsfl(Register dst, Register src);
343 void bsfl(Register dst, const Address& src);
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Dassembler_x86.cc133 void X86Assembler::movl(Register dst, const Immediate& imm) { in movl() argument
135 EmitUint8(0xB8 + dst); in movl()
140 void X86Assembler::movl(Register dst, Register src) { in movl() argument
143 EmitRegisterOperand(src, dst); in movl()
147 void X86Assembler::movl(Register dst, const Address& src) { in movl() argument
150 EmitOperand(dst, src); in movl()
154 void X86Assembler::movl(const Address& dst, Register src) { in movl() argument
157 EmitOperand(src, dst); in movl()
161 void X86Assembler::movl(const Address& dst, const Immediate& imm) { in movl() argument
164 EmitOperand(0, dst); in movl()
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/art/compiler/optimizing/
Dcode_generator_vector_x86_64.cc59 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReplicateScalar() local
63 __ xorps(dst, dst); in VisitVecReplicateScalar()
72 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
73 __ punpcklbw(dst, dst); in VisitVecReplicateScalar()
74 __ punpcklwd(dst, dst); in VisitVecReplicateScalar()
75 __ pshufd(dst, dst, Immediate(0)); in VisitVecReplicateScalar()
80 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
81 __ punpcklwd(dst, dst); in VisitVecReplicateScalar()
82 __ pshufd(dst, dst, Immediate(0)); in VisitVecReplicateScalar()
86 __ movd(dst, locations->InAt(0).AsRegister<CpuRegister>(), /*64-bit*/ false); in VisitVecReplicateScalar()
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Dcode_generator_vector_x86.cc64 XmmRegister dst = locations->Out().AsFpuRegister<XmmRegister>(); in VisitVecReplicateScalar() local
68 __ xorps(dst, dst); in VisitVecReplicateScalar()
77 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
78 __ punpcklbw(dst, dst); in VisitVecReplicateScalar()
79 __ punpcklwd(dst, dst); in VisitVecReplicateScalar()
80 __ pshufd(dst, dst, Immediate(0)); in VisitVecReplicateScalar()
85 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
86 __ punpcklwd(dst, dst); in VisitVecReplicateScalar()
87 __ pshufd(dst, dst, Immediate(0)); in VisitVecReplicateScalar()
91 __ movd(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
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Dcode_generator_vector_mips.cc52 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
58 __ FillB(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
63 __ FillH(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
67 __ FillW(dst, locations->InAt(0).AsRegister<Register>()); in VisitVecReplicateScalar()
77 __ ReplicateFPToVectorRegister(dst, FTMP, /* is_double */ true); in VisitVecReplicateScalar()
81 __ ReplicateFPToVectorRegister(dst, in VisitVecReplicateScalar()
87 __ ReplicateFPToVectorRegister(dst, in VisitVecReplicateScalar()
185 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecReduce() local
193 __ IlvlD(dst, tmp, tmp); in VisitVecReduce()
194 __ AddvW(dst, dst, tmp); in VisitVecReduce()
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Dcode_generator_vector_mips64.cc57 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
63 __ FillB(dst, locations->InAt(0).AsRegister<GpuRegister>()); in VisitVecReplicateScalar()
68 __ FillH(dst, locations->InAt(0).AsRegister<GpuRegister>()); in VisitVecReplicateScalar()
72 __ FillW(dst, locations->InAt(0).AsRegister<GpuRegister>()); in VisitVecReplicateScalar()
76 __ FillD(dst, locations->InAt(0).AsRegister<GpuRegister>()); in VisitVecReplicateScalar()
80 __ ReplicateFPToVectorRegister(dst, in VisitVecReplicateScalar()
86 __ ReplicateFPToVectorRegister(dst, in VisitVecReplicateScalar()
183 VectorRegister dst = VectorRegisterFrom(locations->Out()); in VisitVecReduce() local
191 __ IlvlD(dst, tmp, tmp); in VisitVecReduce()
192 __ AddvW(dst, dst, tmp); in VisitVecReduce()
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Dcode_generator_vector_arm_vixl.cc56 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
62 __ Vdup(Untyped8, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
67 __ Vdup(Untyped16, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
71 __ Vdup(Untyped32, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
137 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce() local
143 __ Vpadd(DataTypeValue::I32, dst, src, src); in VisitVecReduce()
146 __ Vpmin(DataTypeValue::S32, dst, src, src); in VisitVecReduce()
149 __ Vpmax(DataTypeValue::S32, dst, src, src); in VisitVecReduce()
174 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNeg() local
179 __ Vneg(DataTypeValue::S8, dst, src); in VisitVecNeg()
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Dcode_generator_vector_arm64.cc74 VRegister dst = VRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
81 __ Movi(dst.V16B(), Int64ConstantFrom(src_loc)); in VisitVecReplicateScalar()
83 __ Dup(dst.V16B(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
90 __ Movi(dst.V8H(), Int64ConstantFrom(src_loc)); in VisitVecReplicateScalar()
92 __ Dup(dst.V8H(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
98 __ Movi(dst.V4S(), Int64ConstantFrom(src_loc)); in VisitVecReplicateScalar()
100 __ Dup(dst.V4S(), InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
106 __ Movi(dst.V2D(), Int64ConstantFrom(src_loc)); in VisitVecReplicateScalar()
108 __ Dup(dst.V2D(), XRegisterFrom(src_loc)); in VisitVecReplicateScalar()
114 __ Fmov(dst.V4S(), src_loc.GetConstant()->AsFloatConstant()->GetValue()); in VisitVecReplicateScalar()
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Dcode_generator_mips.cc1450 FRegister dst = destination.AsFpuRegister<FRegister>(); in MoveLocation() local
1453 __ Mtc1(src_low, dst); in MoveLocation()
1454 __ MoveToFpuHigh(src_high, dst); in MoveLocation()
1520 Register dst = destination.AsRegister<Register>(); in MoveConstant() local
1521 __ LoadConst32(dst, value); in MoveConstant()
1566 Register dst = destination.AsRegister<Register>(); in MoveConstant() local
1567 __ LoadConst32(dst, value); in MoveConstant()
2047 Register dst = locations->Out().AsRegister<Register>(); in HandleBinaryOp() local
2062 __ Andi(dst, lhs, rhs_imm); in HandleBinaryOp()
2064 __ And(dst, lhs, rhs_reg); in HandleBinaryOp()
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Dcode_generator_mips64.cc1880 GpuRegister dst = locations->Out().AsRegister<GpuRegister>(); in HandleBinaryOp() local
1895 __ Andi(dst, lhs, rhs_imm); in HandleBinaryOp()
1897 __ And(dst, lhs, rhs_reg); in HandleBinaryOp()
1900 __ Ori(dst, lhs, rhs_imm); in HandleBinaryOp()
1902 __ Or(dst, lhs, rhs_reg); in HandleBinaryOp()
1905 __ Xori(dst, lhs, rhs_imm); in HandleBinaryOp()
1907 __ Xor(dst, lhs, rhs_reg); in HandleBinaryOp()
1915 __ Addiu(dst, lhs, rhs_imm); in HandleBinaryOp()
1922 __ Aui(dst, lhs, rhs_imm_high); in HandleBinaryOp()
1924 __ Addiu(dst, dst, rhs_imm_low); in HandleBinaryOp()
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/art/runtime/
Dreflection-inl.h37 JValue* dst) { in ConvertPrimitiveValueNoThrow() argument
40 dst->SetJ(src.GetJ()); in ConvertPrimitiveValueNoThrow()
51 dst->SetS(src.GetI()); in ConvertPrimitiveValueNoThrow()
58 dst->SetI(src.GetI()); in ConvertPrimitiveValueNoThrow()
65 dst->SetJ(src.GetI()); in ConvertPrimitiveValueNoThrow()
72 dst->SetF(src.GetI()); in ConvertPrimitiveValueNoThrow()
75 dst->SetF(src.GetJ()); in ConvertPrimitiveValueNoThrow()
82 dst->SetD(src.GetI()); in ConvertPrimitiveValueNoThrow()
85 dst->SetD(src.GetJ()); in ConvertPrimitiveValueNoThrow()
88 dst->SetD(src.GetF()); in ConvertPrimitiveValueNoThrow()
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/art/runtime/jdwp/
Djdwp_bits.h109 static inline void Write1BE(uint8_t** dst, uint8_t value) { in Write1BE() argument
110 Set1(*dst, value); in Write1BE()
111 *dst += sizeof(value); in Write1BE()
114 static inline void Write2BE(uint8_t** dst, uint16_t value) { in Write2BE() argument
115 Set2BE(*dst, value); in Write2BE()
116 *dst += sizeof(value); in Write2BE()
119 static inline void Write4BE(uint8_t** dst, uint32_t value) { in Write4BE() argument
120 Set4BE(*dst, value); in Write4BE()
121 *dst += sizeof(value); in Write4BE()
124 static inline void Write8BE(uint8_t** dst, uint64_t value) { in Write8BE() argument
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/art/tools/ahat/src/main/com/android/ahat/dominators/
DDominatorsComputation.java140 public Node dst; field in DominatorsComputation.Link
142 public Link(NodeS srcS, Node dst) { in Link() argument
144 this.dst = dst; in Link()
188 NodeS dstS = (NodeS)link.dst.getDominatorsComputationState(); in computeDominators()
193 dstS.node = link.dst; in computeDominators()
200 link.dst.setDominatorsComputationState(dstS); in computeDominators()
202 for (Node child : link.dst.getReferencesForDominators()) { in computeDominators()
/art/runtime/interpreter/mterp/mips/
Dheader.S442 #define SET_VREG_GOTO(rd, rix, dst) \ argument
444 GET_OPCODE_TARGET(dst); \
448 jalr zero, dst; \
452 #define SET_VREG_GOTO(rd, rix, dst) \ argument
454 GET_OPCODE_TARGET(dst); \
461 jalr zero, dst; \
468 #define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ argument
470 GET_OPCODE_TARGET(dst); \
474 jalr zero, dst; \
478 #define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ argument
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/art/test/201-built-in-except-detail-messages/src/
DMain.java136 Integer[] dst = new Integer[10]; in arrayStore() local
137 System.arraycopy(src, 1, dst, 0, 5); in arrayStore()
145 int[] dst = new int[1]; in arrayStore() local
146 System.arraycopy(src, 0, dst, 0, 1); in arrayStore()
153 Runnable[] dst = new Runnable[1]; in arrayStore() local
154 System.arraycopy(src, 0, dst, 0, 1); in arrayStore()
161 double[][] dst = new double[1][]; in arrayStore() local
162 System.arraycopy(src, 0, dst, 0, 1); in arrayStore()
169 Object[] dst = new Object[1]; in arrayStore() local
170 System.arraycopy(src, 0, dst, 0, 1); in arrayStore()
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/art/test/020-string/src/
DMain.java131 char[] dst = new char[7]; in copyTest() local
142 src.getChars(-1, 9, dst, 0); in copyTest()
149 src.getChars(2, 19, dst, 0); in copyTest()
156 src.getChars(2, 1, dst, 0); in copyTest()
163 src.getChars(2, 10, dst, 0); in copyTest()
169 src.getChars(2, 9, dst, 0); in copyTest()
170 System.out.println(new String(dst)); in copyTest()
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc270 ArmManagedRegister dst = dest.AsArm(); in LoadRef() local
271 CHECK(dst.IsCoreRegister() && dst.IsCoreRegister()) << dst; in LoadRef()
273 temps.Exclude(dst.AsVIXLRegister(), base.AsArm().AsVIXLRegister()); in LoadRef()
275 dst.AsVIXLRegister(), in LoadRef()
280 asm_.MaybeUnpoisonHeapReference(dst.AsVIXLRegister()); in LoadRef()
317 ArmManagedRegister dst = m_dst.AsArm(); in LoadRawPtrFromThread() local
318 CHECK(dst.IsCoreRegister()) << dst; in LoadRawPtrFromThread()
320 temps.Exclude(dst.AsVIXLRegister()); in LoadRawPtrFromThread()
321 asm_.LoadFromOffset(kLoadWord, dst.AsVIXLRegister(), tr, offs.Int32Value()); in LoadRawPtrFromThread()
369 ArmManagedRegister dst = m_dst.AsArm(); in Move() local
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/art/libartbase/base/
Dstrlcpy.h31 static inline size_t strlcpy(char* dst, const char* src, size_t size) { in strlcpy() argument
33 return snprintf(dst, size, "%s", src); in strlcpy()
Dsafe_copy.cc31 ssize_t SafeCopy(void *dst, const void *src, size_t len) { in SafeCopy() argument
34 .iov_base = dst, in SafeCopy()
76 UNUSED(dst, src, len); in SafeCopy()
Dsafe_copy_test.cc94 char* dst = static_cast<char*>(dst_map); in TEST() local
95 ASSERT_EQ(0, mprotect(dst + 3 * kPageSize, kPageSize, PROT_NONE)); in TEST()
101 SafeCopy(dst + 1024, src + 512, kPageSize * 3 - 1024)); in TEST()
102 EXPECT_EQ(0, memcmp(dst + 1024, src + 512, kPageSize * 3 - 1024)); in TEST()
/art/test/646-checker-arraycopy-large-cst-pos/src/
DMain.java30 Object[] dst = new Object[2048]; in test() local
34 System.arraycopy(src, 0, dst, 1024, 64); in test()
/art/libdexfile/dex/
Dbase64_test_util.h92 std::unique_ptr<uint8_t[]> dst(new uint8_t[tmp.size()]); in DecodeBase64()
94 std::copy(tmp.begin(), tmp.end(), dst.get()); in DecodeBase64()
95 return dst.release(); in DecodeBase64()
/art/libartbase/base/unix_file/
Drandom_access_file_utils.cc25 bool CopyFile(const RandomAccessFile& src, RandomAccessFile* dst) { in CopyFile() argument
32 if (dst->Write(&buf[0], n, offset) != n) { in CopyFile()

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