| /art/compiler/jni/quick/x86/ |
| D | calling_convention_x86.cc | 157 ManagedRegister in_reg = CurrentParamRegister(); in EntrySpills() local
159 if (!in_reg.IsNoRegister()) { in EntrySpills()
162 ManagedRegisterSpill spill(in_reg, size, spill_offset); in EntrySpills()
166 in_reg = CurrentParamHighLongRegister(); in EntrySpills()
167 DCHECK(!in_reg.IsNoRegister()); in EntrySpills()
169 ManagedRegisterSpill spill2(in_reg, size, spill_offset + 4); in EntrySpills()
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| /art/compiler/jni/quick/ |
| D | jni_compiler.cc | 62 ManagedRegister in_reg);
289 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
290 __ VerifyObject(in_reg, mr_conv->IsCurrentArgPossiblyNull()); in ArtJniCompileMethodInternal()
291 __ StoreRef(handle_scope_offset, in_reg); in ArtJniCompileMethodInternal()
698 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in CopyParameter() local
701 __ CreateHandleScopeEntry(out_reg, handle_scope_offset, in_reg, null_allowed); in CopyParameter()
705 __ Move(out_reg, in_reg, mr_conv->CurrentParamSize()); in CopyParameter()
735 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in CopyParameter() local
748 __ Store(out_off, in_reg, param_size); in CopyParameter()
753 __ StoreSpanning(out_off, in_reg, in_off, mr_conv->InterproceduralScratchRegister()); in CopyParameter()
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 480 X86_64ManagedRegister in_reg = min_reg.AsX86_64(); in CreateHandleScopeEntry() local
481 if (in_reg.IsNoRegister()) { // TODO(64): && null_allowed in CreateHandleScopeEntry()
483 in_reg = out_reg; in CreateHandleScopeEntry()
485 __ movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); in CreateHandleScopeEntry()
487 CHECK(in_reg.IsCpuRegister()); in CreateHandleScopeEntry()
489 VerifyObject(in_reg, null_allowed); in CreateHandleScopeEntry()
492 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
495 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in CreateHandleScopeEntry()
527 X86_64ManagedRegister in_reg = min_reg.AsX86_64(); in LoadReferenceFromHandleScope() local
529 CHECK(in_reg.IsCpuRegister()); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_x86_64.h | 157 ManagedRegister in_reg,
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 429 X86ManagedRegister in_reg = min_reg.AsX86(); in CreateHandleScopeEntry() local
430 CHECK(in_reg.IsCpuRegister()); in CreateHandleScopeEntry()
432 VerifyObject(in_reg, null_allowed); in CreateHandleScopeEntry()
435 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
438 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in CreateHandleScopeEntry()
470 X86ManagedRegister in_reg = min_reg.AsX86(); in LoadReferenceFromHandleScope() local
472 CHECK(in_reg.IsCpuRegister()); in LoadReferenceFromHandleScope()
474 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
477 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in LoadReferenceFromHandleScope()
479 __ movl(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0)); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_x86.h | 134 ManagedRegister in_reg, bool null_allowed) OVERRIDE;
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 562 Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); in CreateHandleScopeEntry() local
564 CHECK(in_reg.IsNoRegister() || in_reg.IsXRegister()) << in_reg; in CreateHandleScopeEntry()
570 if (in_reg.IsNoRegister()) { in CreateHandleScopeEntry()
573 in_reg = out_reg; in CreateHandleScopeEntry()
575 ___ Cmp(reg_w(in_reg.AsOverlappingWRegister()), 0); in CreateHandleScopeEntry()
576 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
609 Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); in LoadReferenceFromHandleScope() local
611 CHECK(in_reg.IsXRegister()) << in_reg; in LoadReferenceFromHandleScope()
613 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
617 ___ Cbz(reg_x(in_reg.AsXRegister()), &exit); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_arm64.h | 147 ManagedRegister in_reg,
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| /art/compiler/jni/quick/x86_64/ |
| D | calling_convention_x86_64.cc | 162 ManagedRegister in_reg = CurrentParamRegister(); in EntrySpills() local
163 if (!in_reg.IsNoRegister()) { in EntrySpills()
166 ManagedRegisterSpill spill(in_reg, size, spill_offset); in EntrySpills()
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 475 ArmManagedRegister in_reg = min_reg.AsArm(); in CreateHandleScopeEntry() local
476 CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()) << in_reg; in CreateHandleScopeEntry()
484 if (in_reg.IsNoRegister()) { in CreateHandleScopeEntry()
489 in_reg = out_reg; in CreateHandleScopeEntry()
492 temps.Exclude(in_reg.AsVIXLRegister()); in CreateHandleScopeEntry()
493 ___ Cmp(in_reg.AsVIXLRegister(), 0); in CreateHandleScopeEntry()
496 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
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| D | jni_macro_assembler_arm_vixl.h | 165 ManagedRegister in_reg,
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| /art/compiler/utils/ |
| D | jni_macro_assembler.h | 182 ManagedRegister in_reg,
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 3938 Mips64ManagedRegister in_reg = min_reg.AsMips64(); in CreateHandleScopeEntry() local
3939 CHECK(in_reg.IsNoRegister() || in_reg.IsGpuRegister()) << in_reg; in CreateHandleScopeEntry()
3946 if (in_reg.IsNoRegister()) { in CreateHandleScopeEntry()
3949 in_reg = out_reg; in CreateHandleScopeEntry()
3951 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
3954 Beqzc(in_reg.AsGpuRegister(), &null_arg); in CreateHandleScopeEntry()
3988 Mips64ManagedRegister in_reg = min_reg.AsMips64(); in LoadReferenceFromHandleScope() local
3990 CHECK(in_reg.IsGpuRegister()) << in_reg; in LoadReferenceFromHandleScope()
3992 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
3995 Beqzc(in_reg.AsGpuRegister(), &null_arg); in LoadReferenceFromHandleScope()
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| D | assembler_mips64.h | 1407 ManagedRegister in_reg, bool null_allowed) OVERRIDE;
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| /art/compiler/optimizing/ |
| D | intrinsics_arm64.cc | 543 FPRegister in_reg = is64bit ? DRegisterFrom(in) : SRegisterFrom(in); in MathAbsFP() local
546 __ Fabs(out_reg, in_reg); in MathAbsFP()
571 Register in_reg = is64bit ? XRegisterFrom(in) : WRegisterFrom(in); in GenAbsInteger() local
574 __ Cmp(in_reg, Operand(0)); in GenAbsInteger()
575 __ Cneg(out_reg, in_reg, lt); in GenAbsInteger()
764 FPRegister in_reg = is_double ? DRegisterFrom(l->InAt(0)) : SRegisterFrom(l->InAt(0)); in GenMathRound() local
770 __ Fcvtas(out_reg, in_reg); in GenMathRound()
778 __ Frinta(tmp_fp, in_reg); in GenMathRound()
779 __ Fsub(tmp_fp, in_reg, tmp_fp); in GenMathRound()
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| D | intrinsics_arm_vixl.cc | 486 vixl32::Register in_reg = RegisterFrom(in); in GenAbsInteger() local
489 __ Asr(mask, in_reg, 31); in GenAbsInteger()
490 __ Add(out_reg, in_reg, mask); in GenAbsInteger()
805 vixl32::SRegister in_reg = InputSRegisterAt(invoke, 0); in VisitMathRoundFloat() local
813 __ Vcvta(S32, F32, temp1, in_reg); in VisitMathRoundFloat()
823 __ Vrinta(F32, F32, temp1, in_reg); in VisitMathRoundFloat()
825 __ Vsub(F32, temp1, in_reg, temp1); in VisitMathRoundFloat()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 5103 MipsManagedRegister in_reg = min_reg.AsMips(); in CreateHandleScopeEntry() local
5104 CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()) << in_reg; in CreateHandleScopeEntry()
5111 if (in_reg.IsNoRegister()) { in CreateHandleScopeEntry()
5114 in_reg = out_reg; in CreateHandleScopeEntry()
5116 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
5119 Beqz(in_reg.AsCoreRegister(), &null_arg); in CreateHandleScopeEntry()
5152 MipsManagedRegister in_reg = min_reg.AsMips(); in LoadReferenceFromHandleScope() local
5154 CHECK(in_reg.IsCoreRegister()) << in_reg; in LoadReferenceFromHandleScope()
5156 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
5159 Beqz(in_reg.AsCoreRegister(), &null_arg); in LoadReferenceFromHandleScope()
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| D | assembler_mips.h | 1339 ManagedRegister in_reg,
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