Home
last modified time | relevance | path

Searched refs:Adc (Results 1 – 22 of 22) sorted by relevance

/external/vixl/test/aarch32/
Dtest-disasm-a32.cc623 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)), in TEST()
1421 COMPARE_BOTH(Adc(r0, r1, 0xbadbeef), in TEST()
1526 COMPARE_BOTH(Adc(r0, r1, -2), "sbc r0, r1, #1\n"); in TEST()
1543 COMPARE_BOTH(Adc(r0, r1, 0xabcd), in TEST()
1547 COMPARE_BOTH(Adc(r0, r1, -0xabcd), in TEST()
1551 COMPARE_BOTH(Adc(r0, r1, 0x1234abcd), in TEST()
1556 COMPARE_BOTH(Adc(r0, r1, -0x1234abcd), in TEST()
1584 COMPARE_T32(Adc(r0, r1, Operand(r2, LSL, r3)), in TEST()
2599 COMPARE_A32(Adc(pc, r0, 1), "adc pc, r0, #1\n"); in TEST()
2600 COMPARE_A32(Adc(r0, pc, 1), "adc r0, pc, #1\n"); in TEST()
[all …]
Dtest-assembler-aarch32.cc243 __ Adc(r4, r2, r3); in TEST() local
244 __ Adc(r5, r0, Operand(r1, LSL, 30)); in TEST() local
245 __ Adc(r6, r0, Operand(r2, LSR, 16)); in TEST() local
246 __ Adc(r7, r2, Operand(r3, ASR, 4)); in TEST() local
247 __ Adc(r8, r2, Operand(r3, ROR, 8)); in TEST() local
248 __ Adc(r9, r2, Operand(r3, RRX)); in TEST() local
271 __ Adc(r5, r2, r3); in TEST() local
272 __ Adc(r6, r0, Operand(r1, LSL, 30)); in TEST() local
273 __ Adc(r7, r0, Operand(r2, LSR, 16)); in TEST() local
274 __ Adc(r8, r2, Operand(r3, ASR, 4)); in TEST() local
[all …]
Dtest-simulator-cond-rd-rn-operand-rm-a32.cc116 M(Adc) \
Dtest-simulator-cond-rd-rn-operand-rm-t32.cc116 M(Adc) \
Dtest-simulator-cond-rd-rn-operand-const-a32.cc116 M(Adc) \
Dtest-simulator-cond-rd-rn-operand-const-t32.cc116 M(Adc) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc116 M(Adc) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc116 M(Adc) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc116 M(Adc) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc116 M(Adc) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc116 M(Adc) \
/external/vixl/test/aarch64/
Dtest-assembler-aarch64.cc8704 __ Adc(x5, x2, Operand(x3)); in TEST() local
8705 __ Adc(x6, x0, Operand(x1, LSL, 60)); in TEST() local
8707 __ Adc(x8, x2, Operand(x3, ASR, 4)); in TEST() local
8708 __ Adc(x9, x2, Operand(x3, ROR, 8)); in TEST() local
8710 __ Adc(w10, w2, Operand(w3)); in TEST() local
8711 __ Adc(w11, w0, Operand(w1, LSL, 30)); in TEST() local
8713 __ Adc(w13, w2, Operand(w3, ASR, 4)); in TEST() local
8714 __ Adc(w14, w2, Operand(w3, ROR, 8)); in TEST() local
8719 __ Adc(x18, x2, Operand(x3)); in TEST() local
8720 __ Adc(x19, x0, Operand(x1, LSL, 60)); in TEST() local
[all …]
/external/swiftshader/third_party/subzero/src/
DIceInstARM32.h381 Adc, enumerator
1003 using InstARM32Adc = InstARM32ThreeAddrGPR<InstARM32::Adc>;
DIceInstX86Base.h76 Adc, enumerator
1389 class InstX86Adc : public InstX86BaseBinopGPR<InstX86Base::Adc> {
1397 : InstX86BaseBinopGPR<InstX86Base::Adc>(Func, Dest, Source) {} in InstX86Adc()
3216 using Adc = typename InstImpl<TraitsType>::InstX86Adc; member
DIceTargetLoweringX86Base.h518 Context.insert<typename Traits::Insts::Adc>(Dest, Src0); in _adc()
DIceInstARM32.cpp3483 template class InstARM32ThreeAddrGPR<InstARM32::Adc>;
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h233 void MacroAssembler::Adc(const Register& rd, in Adc() function
Dmacro-assembler-arm64.h231 inline void Adc(const Register& rd,
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.h989 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) { in Adc() function
1003 void Adc(Register rd, Register rn, const Operand& operand) { in Adc() function
1004 Adc(al, rd, rn, operand); in Adc()
1006 void Adc(FlagsUpdate flags, in Adc() function
1013 Adc(cond, rd, rn, operand); in Adc()
1025 Adc(cond, rd, rn, operand); in Adc()
1030 void Adc(FlagsUpdate flags, in Adc() function
1034 Adc(flags, al, rd, rn, operand); in Adc()
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.cc1726 void MacroAssembler::Adc(const Register& rd, in Adc() function in vixl::aarch64::MacroAssembler
Dmacro-assembler-aarch64.h685 void Adc(const Register& rd, const Register& rn, const Operand& operand);
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc1409 __ Adc(i.OutputRegister32(), i.OutputRegister32(), Operand(0)); in AssembleArchInstruction() local