| /external/llvm/test/Transforms/AtomicExpand/SPARC/ |
| D | partword.ll | 15 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
26 ; CHECK: %8 = load i32, i32* %AlignedAddr
33 ; CHECK: %13 = cmpxchg i32* %AlignedAddr, i32 %12, i32 %11 monotonic monotonic
60 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
71 ; CHECK: %8 = load i32, i32* %AlignedAddr
78 ; CHECK: %13 = cmpxchg i32* %AlignedAddr, i32 %12, i32 %11 monotonic monotonic
106 ; CHECK: %AlignedAddr = inttoptr i64 %1 to i32*
115 ; CHECK: %5 = load i32, i32* %AlignedAddr, align 4
123 ; CHECK: %9 = cmpxchg i32* %AlignedAddr, i32 %loaded, i32 %8 monotonic monotonic
142 ; CHECK: %6 = cmpxchg i32* %AlignedAddr, i32 %loaded, i32 %new monotonic monotonic
[all …]
|
| /external/clang/test/CodeGen/ |
| D | arm-vector-align.c | 14 typedef float AlignedAddr __attribute__ ((aligned (16))); typedef
15 void t1(AlignedAddr *addr1, AlignedAddr *addr2) { in t1()
|
| /external/llvm/include/llvm/Support/ |
| D | Allocator.h | 240 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
241 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
242 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
250 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
251 assert(AlignedAddr + Size <= (uintptr_t)End && in Allocate()
253 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
|
| /external/swiftshader/third_party/llvm-subzero/include/llvm/Support/ |
| D | Allocator.h | 243 uintptr_t AlignedAddr = alignAddr(NewSlab, Alignment); in Allocate() local
244 assert(AlignedAddr + Size <= (uintptr_t)NewSlab + PaddedSize); in Allocate()
245 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
253 uintptr_t AlignedAddr = alignAddr(CurPtr, Alignment); in Allocate() local
254 assert(AlignedAddr + Size <= (uintptr_t)End && in Allocate()
256 char *AlignedPtr = (char*)AlignedAddr; in Allocate()
|
| /external/llvm/lib/CodeGen/ |
| D | AtomicExpandPass.cpp | 567 Value *AlignedAddr; member
614 Ret.AlignedAddr = Builder.CreateIntToPtr( in createMaskInstrs()
719 insertRMWCmpXchgLoop(Builder, PMV.WordType, PMV.AlignedAddr, MemOpOrder, in expandPartwordAtomicRMW()
796 LoadInst *InitLoaded = Builder.CreateLoad(PMV.WordType, PMV.AlignedAddr); in expandPartwordCmpXchg()
810 PMV.AlignedAddr, FullWord_Cmp, FullWord_NewVal, CI->getSuccessOrdering(), in expandPartwordCmpXchg()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 963 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); in EmitAtomicBinaryPartword() local
1017 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) in EmitAtomicBinaryPartword()
1049 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); in EmitAtomicBinaryPartword()
1073 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); in EmitAtomicBinaryPartword()
1184 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); in EmitAtomicCmpSwapPartword() local
1245 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) in EmitAtomicCmpSwapPartword()
1268 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); in EmitAtomicCmpSwapPartword()
1285 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); in EmitAtomicCmpSwapPartword()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1245 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicBinaryPartword() local
1307 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr) in emitAtomicBinaryPartword()
1346 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); in emitAtomicBinaryPartword()
1370 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); in emitAtomicBinaryPartword()
1500 unsigned AlignedAddr = RegInfo.createVirtualRegister(RCp); in emitAtomicCmpSwapPartword() local
1570 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr) in emitAtomicCmpSwapPartword()
1601 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0); in emitAtomicCmpSwapPartword()
1618 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); in emitAtomicCmpSwapPartword()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 3233 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_LOAD_OP() local
3262 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
3337 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr, in lowerATOMIC_CMP_SWAP() local
3353 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift, in lowerATOMIC_CMP_SWAP()
|