Home
last modified time | relevance | path

Searched refs:Ands (Results 1 – 19 of 19) sorted by relevance

/external/vixl/test/aarch32/
Dtest-assembler-aarch32.cc551 __ Ands(r0, r1, r1); in TEST() local
563 __ Ands(r0, r0, Operand(r1, LSL, 4)); in TEST() local
575 __ Ands(r0, r0, Operand(r1, LSR, 4)); in TEST() local
587 __ Ands(r0, r0, Operand(r1, ASR, 4)); in TEST() local
599 __ Ands(r0, r0, Operand(r1, ROR, 1)); in TEST() local
613 __ Ands(r2, r0, Operand(r1, RRX)); in TEST() local
628 __ Ands(r2, r0, Operand(r1, RRX)); in TEST() local
639 __ Ands(r0, r0, 0xf); in TEST() local
650 __ Ands(r0, r0, 0x80000000); in TEST() local
3279 __ Ands(r0, r0, 0); in TEST() local
Dtest-simulator-cond-rd-rn-operand-rm-a32.cc121 M(Ands) \
Dtest-simulator-cond-rd-rn-operand-rm-t32.cc121 M(Ands) \
Dtest-simulator-cond-rd-rn-operand-const-a32.cc121 M(Ands) \
Dtest-simulator-cond-rd-rn-operand-const-t32.cc121 M(Ands) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc121 M(Ands) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc121 M(Ands) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc121 M(Ands) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc121 M(Ands) \
Dtest-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc121 M(Ands) \
Dtest-disasm-a32.cc1592 COMPARE_T32(Ands(r3, r2, Operand(r2, LSR, r2)), in TEST()
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.cc738 void MacroAssembler::Ands(const Register& rd, in Ands() function in vixl::aarch64::MacroAssembler
748 Ands(AppropriateZeroRegFor(rn), rn, operand); in Tst()
Dmacro-assembler-aarch64.h649 void Ands(const Register& rd, const Register& rn, const Operand& operand);
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc958 __ Ands(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local
973 __ Ands(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
/external/v8/src/arm64/
Dmacro-assembler-arm64-inl.h55 void MacroAssembler::Ands(const Register& rd, in Ands() function
Dmacro-assembler-arm64.h177 inline void Ands(const Register& rd,
Dcode-stubs-arm64.cc1467 __ Ands(string_encoding, string_type, kStringEncodingMask); in Generate()
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.h1190 Ands(cond, rd, rn, operand); in And()
1201 Ands(cond, rd, rn, operand); in And()
1215 void Ands(Condition cond, Register rd, Register rn, const Operand& operand) { in Ands() function
1225 void Ands(Register rd, Register rn, const Operand& operand) { in Ands() function
1226 Ands(al, rd, rn, operand); in Ands()
/external/vixl/test/aarch64/
Dtest-assembler-aarch64.cc929 __ Ands(w0, w1, Operand(w1)); in TEST() local
940 __ Ands(w0, w0, Operand(w1, LSR, 4)); in TEST() local
951 __ Ands(x0, x0, Operand(x1, ROR, 1)); in TEST() local
961 __ Ands(w0, w0, Operand(0xf)); in TEST() local
971 __ Ands(w0, w0, Operand(0x80000000)); in TEST() local