| /external/llvm/test/CodeGen/Mips/ |
| D | assertzext-trunc.ll | 17 ; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8)
35 ; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32))
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 57 AssertSext, AssertZext, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 57 AssertSext, AssertZext, enumerator
|
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 202 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerFormalArguments()
406 Val = DAG.getNode(ISD::AssertZext, dl, RV.getLocVT(), Val, in LowerCall()
|
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 357 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, in LowerCCCArguments()
540 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 53 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
162 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(), in PromoteIntRes_AssertZext()
369 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
379 return DAG.getNode(ISD::AssertZext, dl, in PromoteIntRes_FP32_TO_FP16()
1098 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
1668 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
1672 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
|
| D | SelectionDAG.cpp | 1944 case ISD::AssertZext: { in ComputeMaskedBits()
2109 case ISD::AssertZext: in ComputeNumSignBits()
2815 case ISD::AssertZext: { in getNode()
5897 case ISD::AssertZext: return "AssertZext"; in getOperationName()
|
| D | SelectionDAGBuilder.cpp | 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
4366 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ in getTruncatedArgReg()
6460 AssertOp = ISD::AssertZext; in LowerCallTo()
6688 AssertOp = ISD::AssertZext; in LowerArguments()
|
| D | SelectionDAGISel.cpp | 2048 case ISD::AssertZext: in SelectCodeCommon()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 86 case ISD::AssertZext: return "AssertZext"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
182 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
436 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res, in PromoteIntRes_FP_TO_XINT()
1313 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break; in ExpandIntegerResult()
1919 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, in ExpandIntRes_AssertZext()
1923 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); in ExpandIntRes_AssertZext()
|
| D | SelectionDAGBuilder.cpp | 728 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, in getCopyFromRegs()
4659 case ISD::AssertZext: in getUnderlyingArgReg()
7162 SDValue ZExt = DAG.getNode(ISD::AssertZext, SL, Op.getValueType(), in lowerRangeToAssertZExt()
7754 AssertOp = ISD::AssertZext; in LowerCallTo()
8018 AssertOp = ISD::AssertZext; in LowerArguments()
|
| D | TargetLowering.cpp | 1092 case ISD::AssertZext: { in SimplifyDemandedBits()
1729 if (Op0.getOpcode() == ISD::AssertZext && in SimplifySetCC()
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 193 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 427 setTargetDAGCombine(ISD::AssertZext); in MipsTargetLowering()
816 if (N0.getOperand(0).getOpcode() != ISD::AssertZext) in performAssertZextCombine()
829 ISD::AssertZext, SDLoc(N), WiderAssertZext.getValueType(), in performAssertZextCombine()
859 case ISD::AssertZext: in PerformDAGCombine()
2943 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3005 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); in UnpackFromArgumentSlot()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 762 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg, in LowerFormalArguments()
1311 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI, in LowerFrameIndex()
1631 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param, in lowerImplicitZextParam()
3186 if (Op.getOpcode() == ISD::AssertZext) in isFrameIndexOp()
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| D | AMDGPUISelDAGToDAG.cpp | 1513 if (It->getOpcode() == ISD::AssertZext && FI->hasOneUse()) { in PreprocessISelDAG()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 921 Opcode = ISD::AssertZext; in LowerFormalArguments()
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| D | AlphaISelLowering.cpp | 377 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, in LowerCallResult()
|
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 349 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | README-SSE.txt | 497 SSE4 extract-to-mem ops aren't being pattern matched because of the AssertZext
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1471 case ISD::AssertZext: in isValueExtension()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 458 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, in LowerCCCArguments()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.cpp | 458 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 624 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments_64()
1394 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, in LowerCall_64()
|