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Searched refs:BH (Results 1 – 25 of 387) sorted by relevance

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/external/llvm/unittests/ObjectYAML/
DYAMLTest.cpp24 static void mapping(IO &IO, BinaryHolder &BH) { in mapping()
25 IO.mapRequired("Binary", BH.Binary); in mapping()
32 BinaryHolder BH; in TEST() local
36 YOut << BH; in TEST()
/external/swiftshader/third_party/LLVM/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
10 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
29 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
/external/llvm/test/CodeGen/Generic/
Di128-addsub.ll3 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
10 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
22 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
29 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
/external/swiftshader/third_party/LLVM/test/CodeGen/Blackfin/
Daddsub-i128.ll6 define void @test_add(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
13 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
25 define void @test_sub(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
32 %tmp89 = zext i64 %BH to i128 ; <i128> [#uses=1]
/external/llvm/test/CodeGen/Hexagon/
Dsube.ll12 define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
19 %tmp89 = zext i64 %BH to i128
Dadde.ll17 define void @check_adde_addc (i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {
24 %tmp89 = zext i64 %BH to i128
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX, in initLLVMToSEHAndCVRegMapping()
299 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
300 return X86::BH; in getX86SubSuperRegisterOrZero()
311 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
348 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
384 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
420 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegisterOrZero()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.td70 def BH : Register<"bh">;
77 def BX : RegisterWithSubRegs<"bx", [BL,BH]>;
283 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
289 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
291 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
338 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
368 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
369 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
DX86RegisterInfo.cpp675 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
676 return X86::BH; in getX86SubSuperRegister()
687 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
724 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
760 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
796 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: in getX86SubSuperRegister()
/external/llvm/test/CodeGen/X86/
Dnorex-subreg.ll7 ; %R8B<def> = COPY %BH, %EBX<imp-use,kill>
10 ; The register allocation above is invalid, %BH can only be encoded without an
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dnorex-subreg.ll7 ; %R8B<def> = COPY %BH, %EBX<imp-use,kill>
10 ; The register allocation above is invalid, %BH can only be encoded without an
/external/llvm/test/MC/ARM/
Dthumb2-ldrb-ldrh.s4 @ Thumb2 LDRS?[BH] are not valid when Rt == PC (these encodings are used for
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td58 def BH : X86Reg<"bh", 7>;
81 def BX : X86Reg<"bx", 3, [BL,BH]>;
323 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
329 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
331 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
370 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
382 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
383 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
/external/honggfuzz/examples/apache-httpd/corpus_http2/
D4b7938fa3b4d49f54c479dc2f03d5b08.00001a3c.honggfuzz.cov23 …6��2<I�شM�A��pܶ���G�NF�E�m}���뉕^P��B(�����}�+�zJ� �//x���!(��?=�n�Q�BH��i��ϰ�M�v��� H���m…
30 …6��2<I�شM�A��pܶ���G�NF�E�m}���뉕^P��B(�����}�+�zJ� �//x���!(��?=�n�Q�BH��i��ϰ�M�v��� H���m…
37 …6��2<I�شM�A��pܶ���G�NF�E�m}���뉕^P��B(�����}�+�zJ� �//x���!(��?=�n�Q�BH��i��ϰ�M�v��� H���m…
/external/icu/icu4c/source/data/region/
Dnus.txt24 BH{"Ba̱reen"}
Dckb.txt28 BH{"بەحرەین"}
Dshi.txt25 BH{"ⴱⵃⵔⴰⵢⵏ"}
Dzgh.txt25 BH{"ⴱⵃⵔⴰⵢⵏ"}
Dpt_PT.txt16 BH{"Barém"}
Ddyo.txt24 BH{"Bahrayn"}
Dbrx.txt57 BH{"बहरैन"}
Dks.txt57 BH{"بحریٖن"}
/external/lzma/Asm/x86/
D7zAsm.asm63 x3_H equ BH
/external/libphonenumber/
Drelease_notes.txt116 BE, BF, BG, BH, BI, BJ, BL, BM, BN, BO, BQ, BR, BS, BT, BW, BY, BZ, CA, CC,
202 - Updated phone metadata for region code(s): AZ, BH, HN, IN, US
476 AR, BH, BY, CI, CN, GH, KR, KW, LU, ME, NZ, SB, WS
486 BD, BH, EH, GH, IN, JM, LU, MA, MY, NF, NG, PK, SB, TT, TZ
632 BF, BH, BR, CN, GR, IN, MY, PA, TN, US
678 AF, AG, AI, AM, AR, AS, AW, AZ, BD, BH, BI, BM, BO, BQ, BT, BW, BY, CA, CH,
730 YE, OM, PS, AE, IL, BH, QA, BT, NP, IR, TJ, TM, AZ, GE, KG and UZ in English.
799 AR, BF, BH, BR, BY, CH, CM, CN, GE, GW, HN, JM, KH, LT, LU, MU, NP, RO, SO
821 BF, BH, BI, BJ, BR, CR, EH, GA, GE, GN, GU, IL, IN, IR, KH, KW, KZ, MA, MT,
839 AS, BG, BH, BJ, BL, CD, CI, DE, DZ, EH, FJ, GF, GP, IN, KH, KZ, MA, MD, MF,
[all …]
/external/ImageMagick/PerlMagick/t/
Dinput_gray_lsb_08bit.mat6 5F=TV_TeNYVSWPMRQQUVVTTVPNPNZlgVJROF?BH;;;JKMG<84667:845==;;6233/&

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