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Searched refs:BITFIELD64_RANGE (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/compiler/
Dshader_enums.h162 #define VERT_BIT_ALL BITFIELD64_RANGE(0, VERT_ATTRIB_MAX)
165 #define VERT_BIT_FF_ALL BITFIELD64_RANGE(0, VERT_ATTRIB_FF_MAX)
168 BITFIELD64_RANGE(VERT_ATTRIB_TEX(0), VERT_ATTRIB_TEX_MAX)
172 BITFIELD64_RANGE(VERT_ATTRIB_GENERIC(0), VERT_ATTRIB_GENERIC_MAX)
282 #define VARYING_BITS_TEX_ANY BITFIELD64_RANGE(VARYING_SLOT_TEX0, \
/external/mesa3d/src/mesa/swrast_setup/
Dss_context.c146 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) in setup_vertex_format()
157 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_GENERIC0, _TNL_NUM_GENERIC)) { in setup_vertex_format()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dr200_swtcl.c102 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) ) { in r200SetVertexFormat()
162 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in r200SetVertexFormat()
257 if ((0 == (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) in r200ChooseVertexState()
263 if (tnl->render_inputs_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in r200ChooseVertexState()
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_swtcl.c113 (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX))) { in radeonSetVertexFormat()
176 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in radeonSetVertexFormat()
296 (BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX) in radeonChooseVertexState()
/external/mesa3d/src/mesa/drivers/dri/i915/
Di830_vtbl.c96 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in i830_render_start()
127 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { in i830_render_start()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_context.h346 (BITFIELD64_RANGE(0, VARYING_SLOT_MAX) & \
/external/mesa3d/src/mesa/main/
Dmtypes.h69 #define BITFIELD64_RANGE(b, count) \ macro