| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 179 BUILD_PAIR, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 185 BUILD_PAIR, enumerator
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| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 678 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
686 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
701 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
741 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in ExpandADDSUB()
1471 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 691 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
699 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
714 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
756 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in ExpandADDSUB()
1793 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeFloatTypes.cpp | 60 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
119 return DAG.getNode(ISD::BUILD_PAIR, N->getDebugLoc(), in SoftenFloatRes_BUILD_PAIR()
843 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandFloatResult()
1204 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); in ExpandFloatRes_XINT_TO_FP()
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| D | LegalizeIntegerTypes.cpp | 56 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
760 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; in PromoteIntegerOperand()
1091 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | SelectionDAG.cpp | 754 case ISD::BUILD_PAIR: { in VerifyNodeCommon()
2917 if (N1.getOpcode() == ISD::BUILD_PAIR) in getNode()
6082 case ISD::BUILD_PAIR: return "build_pair"; in getOperationName()
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| D | SelectionDAGBuilder.cpp | 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
6711 if (!EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { in LowerArguments()
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| D | DAGCombiner.cpp | 1085 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); in visit()
4912 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
5081 if (N0.getOpcode() == ISD::BUILD_PAIR) { in visitBITCAST()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinISelLowering.cpp | 493 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi)); in ReplaceNodeResults()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 304 case ISD::BUILD_PAIR: return "build_pair"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 72 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
140 return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), in SoftenFloatRes_BUILD_PAIR()
1010 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandFloatResult()
1444 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); in ExpandFloatRes_XINT_TO_FP()
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| D | LegalizeTypesGeneric.cpp | 144 Vals.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, in ExpandRes_BITCAST()
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| D | LegalizeIntegerTypes.cpp | 58 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
886 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; in PromoteIntegerOperand()
1306 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandIntegerResult()
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| D | DAGCombiner.cpp | 1403 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); in visit()
7313 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
7493 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); in visitBITCAST()
7562 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); in visitBITCAST()
7581 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
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| D | SelectionDAGBuilder.cpp | 169 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
200 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
8041 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { in LowerArguments()
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| D | SelectionDAG.cpp | 678 case ISD::BUILD_PAIR: { in VerifySDNode()
3743 if (N1.getOpcode() == ISD::BUILD_PAIR) in getNode()
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 207 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments()
262 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 363 case ISD::BUILD_PAIR: { in Select()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 444 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
503 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 276 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
4636 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3236 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
3427 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
4931 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); in ReplaceATOMIC_OP_64()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | README.txt | 1489 constructed BUILD_PAIR which represents the cast value.
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4395 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0), in ExpandREAD_REGISTER()
4494 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
4867 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
7095 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32, in ReplaceREADCYCLECOUNTER()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 390 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in SPUTargetLowering()
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