| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenExtract.cpp | 148 unsigned BW = Ty->getPrimitiveSizeInBits(); in INITIALIZE_PASS_DEPENDENCY() local
149 if (BW != 32 && BW != 64) in INITIALIZE_PASS_DEPENDENCY()
161 APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL); in INITIALIZE_PASS_DEPENDENCY()
172 uint32_t U = BW - std::max(SL, SR); in INITIALIZE_PASS_DEPENDENCY()
187 APInt C = APInt::getHighBitsSet(BW, BW-U); in INITIALIZE_PASS_DEPENDENCY()
199 Intrinsic::ID IntId = (BW == 32) ? Intrinsic::hexagon_S2_extractu in INITIALIZE_PASS_DEPENDENCY()
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| D | HexagonBitTracker.cpp | 225 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate() argument
228 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
230 while (I*BW < Ws) { in evaluate()
231 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
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| D | BitTracker.cpp | 335 uint16_t BW = RC->getSize()*8; in getRegBitWidth() local
336 return BW; in getRegBitWidth()
342 uint16_t BW = getRegBitWidth(RR); in getCell() local
347 return RegisterCell::self(0, BW); in getCell()
354 return RegisterCell::self(0, BW); in getCell()
364 return RegisterCell::top(BW); in getCell()
426 uint16_t BW = A.getBitWidth(); in eIMM() local
427 assert((unsigned)BW == A.getBitWidth() && "BitWidth overflow"); in eIMM()
428 RegisterCell Res(BW); in eIMM()
429 for (uint16_t i = 0; i < BW; ++i) in eIMM()
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| /external/libvncserver/examples/ |
| D | pnmshow.c | 22 enum { BW, GRAY, TRUECOLOUR } picType=TRUECOLOUR; in main() enumerator
41 picType=BW; in main()
56 if(picType!=BW) in main()
108 case BW: in main()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | Float2Int.cpp | 195 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in walkBackwards() local
196 APInt Min = APInt::getMinValue(BW).zextOrSelf(MaxIntegerBW+1); in walkBackwards()
197 APInt Max = APInt::getMaxValue(BW).zextOrSelf(MaxIntegerBW+1); in walkBackwards()
204 unsigned BW = I->getOperand(0)->getType()->getPrimitiveSizeInBits(); in walkBackwards() local
205 APInt SMin = APInt::getSignedMinValue(BW).sextOrSelf(MaxIntegerBW+1); in walkBackwards()
206 APInt SMax = APInt::getSignedMaxValue(BW).sextOrSelf(MaxIntegerBW+1); in walkBackwards()
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| /external/llvm/include/llvm/ADT/ |
| D | BitVector.h | 552 BitWord BW = Bits[i]; in applyMask() local
557 if (AddBits) BW |= BitWord(M) << b; in applyMask()
558 else BW &= ~(BitWord(M) << b); in applyMask()
560 Bits[i] = BW; in applyMask()
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| /external/swiftshader/third_party/llvm-subzero/include/llvm/ADT/ |
| D | BitVector.h | 552 BitWord BW = Bits[i]; in applyMask() local
557 if (AddBits) BW |= BitWord(M) << b; in applyMask()
558 else BW &= ~(BitWord(M) << b); in applyMask()
560 Bits[i] = BW; in applyMask()
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| /external/icu/icu4c/source/data/region/ |
| D | de_CH.txt | 6 BW{"Botswana"}
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| D | zh_Hant_HK.txt | 20 BW{"博茨瓦納"}
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| D | nus.txt | 33 BW{"Bothiwaana"}
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| D | ckb.txt | 35 BW{"بۆتسوانا"}
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| D | yi.txt | 52 BW{"באצוואַנע"}
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| D | shi.txt | 34 BW{"ⴱⵓⵜⵙⵡⴰⵏⴰ"}
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| D | zgh.txt | 34 BW{"ⴱⵓⵜⵙⵡⴰⵏⴰ"}
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| D | dyo.txt | 33 BW{"Boswana"}
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| D | brx.txt | 68 BW{"बोत्स्वाना"}
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| D | ks.txt | 69 BW{"بوتَسوانا"}
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| D | tg.txt | 39 BW{"Ботсвана"}
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| D | tt.txt | 38 BW{"Ботсвана"}
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 312 unsigned BW = SVT.getSizeInBits(); in ExpandUINT_TO_FLOAT() local
313 SDValue HalfWord = DAG.getConstant(BW/2, VT); in ExpandUINT_TO_FLOAT()
322 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType()); in ExpandUINT_TO_FLOAT()
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| /external/fio/ |
| D | STEADYSTATE-TODO | 7 - Report read, write, trim IOPS/BW separately
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceBitVector.h | 789 BitWord BW = Bits[i]; in applyMask() local
796 BW |= BitWord(M) << b; in applyMask()
798 BW &= ~(BitWord(M) << b); in applyMask()
800 Bits[i] = BW; in applyMask()
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| /external/skia/src/sfnt/ |
| D | SkOTTable_EBLC.h | 57 BW = 1, enumerator
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| /external/skqp/src/sfnt/ |
| D | SkOTTable_EBLC.h | 57 BW = 1, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 778 unsigned BW = VT.getScalarType().getSizeInBits(); in ExpandSEXTINREG() local
780 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT); in ExpandSEXTINREG()
991 unsigned BW = SVT.getSizeInBits(); in ExpandUINT_TO_FLOAT() local
992 SDValue HalfWord = DAG.getConstant(BW/2, DL, VT); in ExpandUINT_TO_FLOAT()
1001 SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType()); in ExpandUINT_TO_FLOAT()
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