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Searched refs:COND (Results 1 – 25 of 84) sorted by relevance

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/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_rs.c45 unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2); in etna_compile_rs_state()
46 unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2); in etna_compile_rs_state()
49 int source_multi = COND(rs->source_tiling & ETNA_LAYOUT_BIT_MULTI, 1); in etna_compile_rs_state()
50 int dest_multi = COND(rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI, 1); in etna_compile_rs_state()
61 COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) | in etna_compile_rs_state()
62 COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) | in etna_compile_rs_state()
63 COND(rs->source_tiling & 1, VIVS_RS_CONFIG_SOURCE_TILED) | in etna_compile_rs_state()
65 COND(rs->dest_tiling & 1, VIVS_RS_CONFIG_DEST_TILED) | in etna_compile_rs_state()
66 COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) | in etna_compile_rs_state()
67 COND(rs->flip, VIVS_RS_CONFIG_FLIP); in etna_compile_rs_state()
[all …]
Detnaviv_asm.c73 COND(inst->sat, VIV_ISA_WORD_0_SAT) | in etna_assemble()
74 COND(inst->dst.use, VIV_ISA_WORD_0_DST_USE) | in etna_assemble()
81 COND(inst->src[0].use, VIV_ISA_WORD_1_SRC0_USE) | in etna_assemble()
83 COND(inst->type & 0x4, VIV_ISA_WORD_1_TYPE_BIT2) | in etna_assemble()
85 COND(inst->src[0].neg, VIV_ISA_WORD_1_SRC0_NEG) | in etna_assemble()
86 COND(inst->src[0].abs, VIV_ISA_WORD_1_SRC0_ABS); in etna_assemble()
89 COND(inst->src[1].use, VIV_ISA_WORD_2_SRC1_USE) | in etna_assemble()
92 COND(inst->src[1].neg, VIV_ISA_WORD_2_SRC1_NEG) | in etna_assemble()
93 COND(inst->src[1].abs, VIV_ISA_WORD_2_SRC1_ABS) | in etna_assemble()
97 COND(inst->src[2].use, VIV_ISA_WORD_3_SRC2_USE) | in etna_assemble()
[all …]
Detnaviv_rasterizer.c57 COND(so->point_quad_rasterization, VIVS_PA_CONFIG_POINT_SPRITE_ENABLE) | in etna_rasterizer_state_create()
58 COND(so->point_size_per_vertex, VIVS_PA_CONFIG_POINT_SIZE_ENABLE) | in etna_rasterizer_state_create()
59 … COND(VIV_FEATURE(ctx->screen, chipMinorFeatures1, WIDE_LINE), VIVS_PA_CONFIG_WIDE_LINE); in etna_rasterizer_state_create()
64 cs->SE_CONFIG = COND(so->line_last_pixel, VIVS_SE_CONFIG_LAST_PIXEL_ENABLE); in etna_rasterizer_state_create()
68 COND(so->half_pixel_center, VIVS_PA_SYSTEM_MODE_UNK0 | VIVS_PA_SYSTEM_MODE_UNK4); in etna_rasterizer_state_create()
Detnaviv_zsa.c98 COND(so->depth.writemask, VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE) | in etna_zsa_state_create()
99 COND(early_z, VIVS_PE_DEPTH_CONFIG_EARLY_Z) | in etna_zsa_state_create()
100 COND(disable_zs, VIVS_PE_DEPTH_CONFIG_DISABLE_ZS); in etna_zsa_state_create()
102 COND(so->alpha.enabled, VIVS_PE_ALPHA_OP_ALPHA_TEST) | in etna_zsa_state_create()
Detnaviv_blend.c75 COND(separate_alpha, VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA) | in etna_blend_state_create()
88 COND(full_overwrite, VIVS_PE_COLOR_FORMAT_OVERWRITE); in etna_blend_state_create()
/external/skqp/include/gpu/
DGrConfig.h144 #define GR_ALWAYSASSERT(COND) \ argument
146 if (!(COND)) { \
147 SkDebugf("%s %s failed\n", GR_FILE_AND_LINE_STR, #COND); \
158 #define GR_DEBUGASSERT(COND) GR_ALWAYSASSERT(COND) argument
160 #define GR_DEBUGASSERT(COND) argument
167 #define GrAlwaysAssert(COND) GR_ALWAYSASSERT(COND) argument
/external/skia/include/gpu/
DGrConfig.h144 #define GR_ALWAYSASSERT(COND) \ argument
146 if (!(COND)) { \
147 SkDebugf("%s %s failed\n", GR_FILE_AND_LINE_STR, #COND); \
158 #define GR_DEBUGASSERT(COND) GR_ALWAYSASSERT(COND) argument
160 #define GR_DEBUGASSERT(COND) argument
167 #define GrAlwaysAssert(COND) GR_ALWAYSASSERT(COND) argument
/external/libopus/silk/
Dtypedef.h57 # define silk_assert(COND) _ASSERTE(COND) argument
72 # define silk_assert(COND) {if (!(COND)) {silk_fatal("assertion failed: " #COND);}} argument
74 # define silk_assert(COND) argument
/external/mesa3d/src/gallium/drivers/freedreno/a5xx/
Dfd5_program.c231 COND(ncomp[0] > 0, A5XX_VPC_SO_BUF_CNTL_BUF0) | in emit_stream_out()
232 COND(ncomp[1] > 0, A5XX_VPC_SO_BUF_CNTL_BUF1) | in emit_stream_out()
233 COND(ncomp[2] > 0, A5XX_VPC_SO_BUF_CNTL_BUF2) | in emit_stream_out()
234 COND(ncomp[3] > 0, A5XX_VPC_SO_BUF_CNTL_BUF3)); in emit_stream_out()
380 COND(s[VS].v, A5XX_HLSQ_VS_CONTROL_REG_ENABLED)); in fd5_program_emit()
383 COND(s[FS].v, A5XX_HLSQ_FS_CONTROL_REG_ENABLED)); in fd5_program_emit()
386 COND(s[HS].v, A5XX_HLSQ_HS_CONTROL_REG_ENABLED)); in fd5_program_emit()
389 COND(s[DS].v, A5XX_HLSQ_DS_CONTROL_REG_ENABLED)); in fd5_program_emit()
392 COND(s[GS].v, A5XX_HLSQ_GS_CONTROL_REG_ENABLED)); in fd5_program_emit()
407 COND(s[VS].v, A5XX_SP_VS_CONTROL_REG_ENABLED)); in fd5_program_emit()
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll8 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
10 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTLZ]]
27 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
29 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTLZ]]
47 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i16 %A, 0
49 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTLZ]]
67 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i64 %A, 0
69 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
87 ; ALL: [[COND:%[A-Za-z0-9]+]] = icmp eq i32 %A, 0
89 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
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/external/mesa3d/src/gallium/drivers/freedreno/a4xx/
Dfd4_program.c319 COND(emit->key.binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS)); in fd4_program_emit()
323 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) | in fd4_program_emit()
324 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) | in fd4_program_emit()
325 COND(s[VS].instrlen && s[FS].instrlen, in fd4_program_emit()
338 COND(s[VS].v->has_samp, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE)); in fd4_program_emit()
388 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) | in fd4_program_emit()
407 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) | in fd4_program_emit()
413 COND(s[FS].v->has_samp, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE)); in fd4_program_emit()
416 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) | in fd4_program_emit()
417 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) | in fd4_program_emit()
[all …]
Dfd4_emit.c427 COND(elem->instance_divisor, A4XX_VFD_FETCH_INSTR_0_INSTANCED) | in fd4_emit_vertex_bufs()
428 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT)); in fd4_emit_vertex_bufs()
441 COND(isint, A4XX_VFD_DECODE_INSTR_INT) | in fd4_emit_vertex_bufs()
442 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT)); in fd4_emit_vertex_bufs()
462 COND(switchnext, A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT)); in fd4_emit_vertex_bufs()
475 COND(switchnext, A4XX_VFD_DECODE_INSTR_SWITCHNEXT)); in fd4_emit_vertex_bufs()
564 COND(clamp, A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE) | in fd4_emit_state()
565 COND(fragz, A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE) | in fd4_emit_state()
566 COND(fragz && fp->frag_coord, A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS)); in fd4_emit_state()
573 COND(fragz, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE) | in fd4_emit_state()
[all …]
/external/valgrind/drd/tests/
Dtsan_unittest.cpp132 int COND = 0; variable
384 COND = 1; in Waker()
392 COND = 0; in Waiter()
395 while(COND != 1) in Waiter()
432 COND = 1; // We are done! Tell the Waiter. in Waker()
438 COND = 0; in Waiter()
440 MU.LockWhen(Condition(&ArgIsOne, &COND)); // calls ANNOTATE_CONDVAR_WAIT in Waiter()
512 COND = 1; in Waker()
520 COND = 0; in Waiter()
524 while(COND != 1) in Waiter()
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/external/mesa3d/src/gallium/drivers/freedreno/a3xx/
Dfd3_program.c242 COND(fp->frag_coord, A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(regid(0,0)) | in fd3_program_emit()
255 COND(emit->key.binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) | in fd3_program_emit()
265 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) | in fd3_program_emit()
334 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) | in fd3_program_emit()
340 COND(fp->has_samp > 0, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) | in fd3_program_emit()
356 COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) | in fd3_program_emit()
363 COND(fp->key.half_precision, A3XX_SP_FS_MRT_REG_HALF_PRECISION); in fd3_program_emit()
367 mrt_reg |= COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) | in fd3_program_emit()
368 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT); in fd3_program_emit()
377 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE)); in fd3_program_emit()
[all …]
Dfd3_emit.c419 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) | in fd3_emit_vertex_bufs()
421 COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) | in fd3_emit_vertex_bufs()
433 COND(isint, A3XX_VFD_DECODE_INSTR_INT) | in fd3_emit_vertex_bufs()
434 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT)); in fd3_emit_vertex_bufs()
454 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) | in fd3_emit_vertex_bufs()
467 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT)); in fd3_emit_vertex_bufs()
509 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS); in fd3_emit_state()
510 val |= COND(fp->frag_coord, A3XX_RB_RENDER_CONTROL_XCOORD | in fd3_emit_state()
578 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE); in fd3_emit_state()
579 val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD | in fd3_emit_state()
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/external/llvm/test/CodeGen/AMDGPU/
Dfract.f64.ll16 ; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
17 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
18 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
43 ; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
44 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
45 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
71 ; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
72 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
73 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
Duniform-cfg.ll34 ; SI-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
35 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
91 ; SI-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
92 ; SI-DAG: s_and_b64 vcc, exec, [[COND]]
122 ; SI: v_cmp_ne_i32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]]
123 ; SI: s_and_b64 vcc, exec, [[COND]]
147 ; SI: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]]
148 ; SI: s_and_b64 vcc, exec, [[COND]]
253 ; SI: s_load_dword [[COND:s[0-9]+]]
254 ; SI: s_cmp_lt_i32 [[COND]], 1
[all …]
/external/llvm/test/Transforms/Inline/
Dguard-intrinsic.ll14 ; CHECK: [[COND:%[^ ]+]] = load volatile i1, i1* %c
15 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND]], i32 1) [ "deopt"(i32 2, i3…
25 ; CHECK: [[COND:%[^ ]+]] = load volatile i1, i1* %c
26 ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 [[COND]], i32 1) [ "deopt"(i32 3, i3…
/external/llvm/test/Transforms/SimplifyCFG/
D2003-08-17-FoldSwitch.ll74 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 %C, 0
75 ; CHECK-NEXT: [[DOT:%.*]] = select i1 [[COND]], i32 1, i32 0
91 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 %C, 0
92 ; CHECK-NEXT: [[DOT:%.*]] = select i1 [[COND]], i32 1, i32 0
/external/mesa3d/src/egl/main/
Deglcompiler.h37 #define STATIC_ASSERT(COND) \ argument
39 (void) sizeof(char [1 - 2*!(COND)]); \
/external/clang/test/CodeGenObjC/
Darc-ternary-op.m7 // CHECK: [[COND:%.*]] = alloca i8,
15 // CHECK-NEXT: [[T0:%.*]] = load i8, i8* [[COND]]
48 // CHECK: [[COND:%.*]] = alloca i32
63 // CHECK-NEXT: [[T0:%.*]] = load i32, i32* [[COND]]
84 // CHECK: [[T0:%.*]] = load i32, i32* [[COND]]
122 // CHECK: [[COND:%.*]] = alloca i32,
127 // CHECK: [[T0:%.*]] = load i32, i32* [[COND]],
/external/chromium-trace/catapult/systrace/atrace_helper/jni/
Dlogging.h13 #define CHECK_ARGS(COND, ERR) \ argument
14 "FAILED CHECK(%s) @ %s:%d (errno: %s)\n", #COND, __FILE__, __LINE__, \
/external/libdrm/
Dlibdrm_macros.h38 #define STATIC_ASSERT(COND) \ argument
40 (void) sizeof(char [1 - 2*!(COND)]); \
/external/clang/include/clang/AST/
DStmt.h882 enum { INIT, VAR, COND, THEN, ELSE, END_EXPR }; enumerator
917 const Expr *getCond() const { return reinterpret_cast<Expr*>(SubExprs[COND]);} in getCond()
918 void setCond(Expr *E) { SubExprs[COND] = reinterpret_cast<Stmt *>(E); } in setCond()
924 Expr *getCond() { return reinterpret_cast<Expr*>(SubExprs[COND]); } in getCond()
959 enum { INIT, VAR, COND, BODY, END_EXPR }; enumerator
994 const Expr *getCond() const { return reinterpret_cast<Expr*>(SubExprs[COND]);} in getCond()
998 Expr *getCond() { return reinterpret_cast<Expr*>(SubExprs[COND]);} in getCond()
999 void setCond(Expr *E) { SubExprs[COND] = reinterpret_cast<Stmt *>(E); } in setCond()
1031 return SubExprs[BODY] ? SubExprs[BODY]->getLocEnd() : SubExprs[COND]->getLocEnd(); in getLocEnd()
1049 enum { VAR, COND, BODY, END_EXPR }; enumerator
[all …]
/external/llvm/test/Transforms/SafeStack/X86/
Dssp.ll19 ; CHECK: %[[COND:.*]] = icmp ne i8* %[[StackGuard]], %[[B]]
20 ; CHECK: br i1 %[[COND]], {{.*}} !prof

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