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Searched refs:CVT_S_W (Results 1 – 13 of 13) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrFPU.td139 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>;
366 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>;
/external/v8/src/mips/
Dconstants-mips.h575 CVT_S_W = ((4U << 3) + 0), enumerator
Ddisasm-mips.cc1001 case CVT_S_W: // Convert word to float (single). in DecodeTypeRegisterWRsType()
Dassembler-mips.cc2843 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); in cvt_s_w()
Dsimulator-mips.cc2948 case CVT_S_W: // Convert word to float (single). in DecodeTypeRegisterWRsType()
/external/v8/src/mips64/
Dconstants-mips64.h604 CVT_S_W = ((4U << 3) + 0), enumerator
Ddisasm-mips64.cc1042 case CVT_S_W: // Convert word to float (single). in DecodeTypeRegisterWRsType()
Dassembler-mips64.cc3093 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); in cvt_s_w()
Dsimulator-mips64.cc3245 case CVT_S_W: // Convert word to float (single). in DecodeTypeRegisterWRsType()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp369 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
DMipsInstrFPU.td308 def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc481 24365U, // CVT_S_W
2195 0U, // CVT_S_W
DMipsGenDisassemblerTables.inc1125 /* 2991 */ MCD_OPC_Decode, 208, 3, 71, // Opcode: CVT_S_W