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Searched refs:Cycle (Results 1 – 25 of 27) sorted by relevance

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/external/kmod/testsuite/rootfs-pristine/test-depmod/detect-loop/
Dcorrect.txt1 depmod: ERROR: Cycle detected: mod_loop_d -> mod_loop_e -> mod_loop_d
2 depmod: ERROR: Cycle detected: mod_loop_i -> mod_loop_j -> mod_loop_k -> mod_loop_h -> mod_loop_i
3 depmod: ERROR: Cycle detected: mod_loop_i -> mod_loop_j -> mod_loop_h -> mod_loop_i
4 depmod: ERROR: Cycle detected: mod_loop_c -> mod_loop_a -> mod_loop_b -> mod_loop_c
/external/llvm/lib/CodeGen/
DMachineTraceMetrics.cpp682 unsigned Cycle; member
688 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {} in LiveRegUnit()
835 unsigned Cycle = 0; in computeInstrDepths() local
848 Cycle = std::max(Cycle, DepCycle); in computeInstrDepths()
852 MICycles.Depth = Cycle; in computeInstrDepths()
855 DEBUG(dbgs() << Cycle << '\t' << UseMI); in computeInstrDepths()
859 TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height); in computeInstrDepths()
860 DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI); in computeInstrDepths()
894 unsigned DepHeight = I->Cycle; in updatePhysDepsUpwards()
913 if (LRU.Cycle <= Height && LRU.MI != &MI) { in updatePhysDepsUpwards()
[all …]
DMachinePipeliner.cpp2227 for (int Cycle = Schedule.getFirstCycle(), in generatePipelinedLoop() local
2229 Cycle <= LastCycle; ++Cycle) { in generatePipelinedLoop()
2230 std::deque<SUnit *> &CycleInstrs = Schedule.getInstructions(Cycle); in generatePipelinedLoop()
3903 for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) { in finalizeSchedule() local
3904 std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[Cycle]; in finalizeSchedule()
DIfConversion.cpp229 unsigned Cycle, unsigned Extra, in MeetIfcvtSizeLimit() argument
231 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra, in MeetIfcvtSizeLimit()
/external/llvm/test/Analysis/TypeBasedAliasAnalysis/
Dcyclic.ll2 ; CHECK: Cycle found in TBAA metadata.
/external/llvm/test/CodeGen/X86/
Drdtsc.ll19 ; Verify that we correctly lower the Read Cycle Counter GCC x86 builtins
/external/llvm/lib/Target/AMDGPU/
DR600InstrInfo.cpp471 unsigned Cycle = getTransSwizzle(TransSwz, i); in isLegalUpTo() local
476 if (Vector[Src.second][Cycle] < 0) in isLegalUpTo()
477 Vector[Src.second][Cycle] = Src.first; in isLegalUpTo()
478 if (Vector[Src.second][Cycle] != Src.first) in isLegalUpTo()
532 unsigned Cycle = getTransSwizzle(TransSwz, i); in isConstCompatible() local
535 if (ConstCount > 0 && Cycle == 0) in isConstCompatible()
537 if (ConstCount > 1 && Cycle == 1) in isConstCompatible()
/external/autotest/client/site_tests/power_LoadTest/
Dcontrol.web_1hour39 # the window. Cycle will cycle through the urls for the duration of the window
Dcontrol.single_page39 # the window. Cycle will cycle through the urls for the duration of the window
Dcontrol.docs_1hour39 # the window. Cycle will cycle through the urls for the duration of the window
Dcontrol.video_1hour39 # the window. Cycle will cycle through the urls for the duration of the window
Dcontrol.email_1hour39 # the window. Cycle will cycle through the urls for the duration of the window
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DScheduleDAG.h476 void setCurCycle(unsigned Cycle) {
477 CurCycle = Cycle;
/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h567 void setCurCycle(unsigned Cycle) {
568 CurCycle = Cycle;
/external/bart/
DREADME.md91 #### Duty Cycle
/external/libchrome/base/posix/
Dfile_descriptor_shuffle_unittest.cc138 TEST(FileDescriptorShuffleTest, Cycle) { in TEST() argument
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DIfConversion.cpp206 unsigned Cycle, unsigned Extra, in MeetIfcvtSizeLimit() argument
208 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra, in MeetIfcvtSizeLimit()
/external/valgrind/docs/internals/
D3_9_BUGSTATUS.txt114 338141 Cachegrind's Cycle Estimation is very different from the
/external/python/cpython2/Doc/c-api/
Dgcsupport.rst16 .. Cycle Collector (XXX not found: ../ext/example-cycle-support.html)".
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp131 int Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency() local
132 if (Cycle < 0) in getInstrLatency()
135 Latency = std::max(Latency, (unsigned) Cycle); in getInstrLatency()
/external/ltp/testcases/kernel/io/disktest/
DCHANGELOG63 Fixed cycle performance stat printing. Cycle performance was printing at
/external/icu/icu4c/source/data/lang/
Den.txt21 hc{"Hour Cycle (12 vs 24)"}
Dar_XB.txt21 hc{"؜‮Hour‬؜ ؜‮Cycle‬؜ (12 ؜‮vs‬؜ 24)"}
/external/google-breakpad/src/common/
Dtest_assembler_unittest.cc225 TEST(AssignmentDeathTest, Cycle) { in TEST() argument
/external/clang/include/clang/Basic/
DDiagnosticSemaKinds.td2668 "Cycle in acquired_before/after dependencies, starting with '%0'">,
4951 let CategoryName = "ARC Retain Cycle" in {
4960 } // end "ARC Retain Cycle" category

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