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/external/llvm/test/CodeGen/AMDGPU/
Dudivrem.ll7 ; EG-DAG: MULHI
8 ; EG-DAG: MULLO_INT
9 ; EG-DAG: SUB_INT
12 ; EG-DAG: ADD_INT
13 ; EG-DAG: SUB_INT
18 ; EG-DAG: SETGE_UINT
19 ; EG-DAG: SETGE_UINT
21 ; EG-DAG: ADD_INT
22 ; EG-DAG: SUB_INT
23 ; EG-DAG: CNDE_INT
[all …]
Dllvm.memcpy.ll9 ; SI-DAG: ds_read_u8
10 ; SI-DAG: ds_read_u8
11 ; SI-DAG: ds_read_u8
12 ; SI-DAG: ds_read_u8
13 ; SI-DAG: ds_read_u8
14 ; SI-DAG: ds_read_u8
15 ; SI-DAG: ds_read_u8
16 ; SI-DAG: ds_read_u8
18 ; SI-DAG: ds_read_u8
19 ; SI-DAG: ds_read_u8
[all …]
Dfp_to_uint.ll46 ; EG-DAG: AND_INT
47 ; EG-DAG: LSHR
48 ; EG-DAG: SUB_INT
49 ; EG-DAG: AND_INT
50 ; EG-DAG: ASHR
51 ; EG-DAG: AND_INT
52 ; EG-DAG: OR_INT
53 ; EG-DAG: SUB_INT
54 ; EG-DAG: LSHL
55 ; EG-DAG: LSHL
[all …]
Dfp_to_sint.ll55 ; EG-DAG: AND_INT
56 ; EG-DAG: LSHR
57 ; EG-DAG: SUB_INT
58 ; EG-DAG: AND_INT
59 ; EG-DAG: ASHR
60 ; EG-DAG: AND_INT
61 ; EG-DAG: OR_INT
62 ; EG-DAG: SUB_INT
63 ; EG-DAG: LSHL
64 ; EG-DAG: LSHL
[all …]
Dfdiv.ll15 ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
16 ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
21 ; SI-DAG: v_rcp_f32
22 ; SI-DAG: v_mul_f32
24 ; I754-DAG: v_div_scale_f32
25 ; I754-DAG: v_rcp_f32
26 ; I754-DAG: v_fma_f32
27 ; I754-DAG: v_mul_f32
28 ; I754-DAG: v_fma_f32
29 ; I754-DAG: v_div_fixup_f32
[all …]
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll32 ; MM-DAG: lui $2, 0
42 ; 32-C-DAG: addiu $2, $zero, 1
43 ; 32-C-DAG: c.eq.s $f12, $f14
46 ; 64-C-DAG: addiu $2, $zero, 1
47 ; 64-C-DAG: c.eq.s $f12, $f13
50 ; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
51 ; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
52 ; 32-CMP-DAG: andi $2, $[[T1]], 1
54 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
55 ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
[all …]
Dmadd-msub.ll14 ; 32-DAG: sra $[[T0:[0-9]+]], $6, 31
15 ; 32-DAG: mtlo $6
16 ; 32-DAG: [[m:m]]add ${{[45]}}, ${{[45]}}
17 ; 32-DAG: [[m]]fhi $2
18 ; 32-DAG: [[m]]flo $3
20 ; DSP-DAG: sra $[[T0:[0-9]+]], $6, 31
21 ; DSP-DAG: mtlo $6, $[[AC:ac[0-3]+]]
22 ; DSP-DAG: madd $[[AC]], ${{[45]}}, ${{[45]}}
23 ; DSP-DAG: mfhi $2, $[[AC]]
24 ; DSP-DAG: mflo $3, $[[AC]]
[all …]
Dcmov.ll14 ; 32-CMOV-DAG: lw $[[R0:[0-9]+]], %got(i3)
15 ; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
16 ; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4
17 ; 32-CMOV-DAG: lw $2, 0($[[R0]])
19 ; 32-CMP-DAG: lw $[[R0:[0-9]+]], %got(i3)
20 ; 32-CMP-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1)
21 ; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $[[R1]], $4
22 ; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[R0]], $4
23 ; 32-CMP-DAG: or $[[T2:[0-9]+]], $[[T0]], $[[T1]]
24 ; 32-CMP-DAG: lw $2, 0($[[T2]])
[all …]
Do32_cc.ll8 ; ALL-DAG: ldc1 $f12, %lo
9 ; ALL-DAG: ldc1 $f14, %lo
20 ; ALL-DAG: lwc1 $f12, %lo
21 ; ALL-DAG: lwc1 $f14, %lo
32 ; ALL-DAG: lwc1 $f12, %lo
33 ; ALL-DAG: ldc1 $f14, %lo
44 ; ALL-DAG: ldc1 $f12, %lo
45 ; ALL-DAG: lwc1 $f14, %lo
56 ; ALL-DAG: addiu $4, $zero, 12
57 ; ALL-DAG: addiu $5, $zero, 13
[all …]
Dbswap.ll16 ; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
17 ; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
18 ; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8
19 ; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
20 ; MIPS16-DAG: li $[[R4:[0-9]+]], 65280
21 ; MIPS16-DAG: and $[[R4]], $[[R0]]
22 ; MIPS16-DAG: or $[[R1]], $[[R4]]
23 ; MIPS16-DAG: lw $[[R7:[0-9]+]], $CPI
24 ; MIPS16-DAG: and $[[R7]], $[[R2]]
25 ; MIPS16-DAG: or $[[R3]], $[[R7]]
[all …]
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dcallabi.ll43 ; ALL-DAG: addiu $4, $zero, 10
44 ; ALL-DAG: lw $25, %got(xi)(${{[0-9]+}})
55 ; ALL-DAG: addiu $[[T0:[0-9]+]], $zero, 76
56 ; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 101
58 ; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T0]], 24
59 ; 32R1-DAG: sra $[[T3:[0-9]+]], $[[T2]], 24
60 ; 32R1-DAG: sll $[[T4:[0-9]+]], $[[T1]], 24
61 ; 32R1-DAG: sra $[[T5:[0-9]+]], $[[T4]], 24
63 ; 32R2-DAG: seb $4, $[[T0]]
64 ; 32R2-DAG: seb $5, $[[T1]]
[all …]
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dfp.arm.call.ll65 ; CHECK-DAG: vmov.f32 s0
68 ; CHECK-DAG: vmov.f32 s0
69 ; CHECK-DAG: vmov.f32 s1
72 ; CHECK-DAG: vmov.f32 s0
73 ; CHECK-DAG: vmov.f32 s1
74 ; CHECK-DAG: vmov.f32 s2
77 ; CHECK-DAG: vmov.f32 s0
78 ; CHECK-DAG: vmov.f32 s1
79 ; CHECK-DAG: vmov.f32 s2
80 ; CHECK-DAG: vmov.f32 s3
[all …]
/external/llvm/test/CodeGen/Mips/cconv/
Darguments-varargs.ll28 ; O32-DAG: sw $7, 20([[SP]])
29 ; O32-DAG: sw $6, 16([[SP]])
30 ; O32-DAG: sw $5, 12([[SP]])
32 ; NEW-DAG: sd $11, 56([[SP]])
33 ; NEW-DAG: sd $10, 48([[SP]])
34 ; NEW-DAG: sd $9, 40([[SP]])
35 ; NEW-DAG: sd $8, 32([[SP]])
36 ; NEW-DAG: sd $7, 24([[SP]])
37 ; NEW-DAG: sd $6, 16([[SP]])
38 ; NEW-DAG: sd $5, 8([[SP]])
[all …]
Dreturn-struct.ll30 ; O32-DAG: lui [[R1:\$[0-9]+]], %hi(struct_byte)
31 ; O32-DAG: lbu $2, %lo(struct_byte)([[R1]])
33 ; N32-LE-DAG: lui [[R1:\$[0-9]+]], %hi(struct_byte)
34 ; N32-LE-DAG: lb $2, %lo(struct_byte)([[R1]])
36 ; N32-BE-DAG: lui [[R1:\$[0-9]+]], %hi(struct_byte)
37 ; N32-BE-DAG: lb [[R2:\$[0-9]+]], %lo(struct_byte)([[R1]])
38 ; N32-BE-DAG: dsll $2, [[R2]], 56
40 ; N64-LE-DAG: ld [[R1:\$[0-9]+]], %got_disp(struct_byte)($1)
41 ; N64-LE-DAG: lb $2, 0([[R1]])
43 ; N64-BE-DAG: ld [[R1:\$[0-9]+]], %got_disp(struct_byte)($1)
[all …]
/external/llvm/test/CodeGen/AArch64/
Dfp16-v4-instructions.ll6 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
7 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
27 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
28 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
39 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
40 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
51 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
52 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
86 ; CHECK-DAG: fcvt
87 ; CHECK-DAG: fcvt
[all …]
Dfp16-v8-instructions.ll8 ; CHECK-DAG: fadd
9 ; CHECK-DAG: fcvt
10 ; CHECK-DAG: fcvt
11 ; CHECK-DAG: fadd
12 ; CHECK-DAG: fcvt
13 ; CHECK-DAG: fcvt
14 ; CHECK-DAG: fadd
15 ; CHECK-DAG: fcvt
16 ; CHECK-DAG: fcvt
17 ; CHECK-DAG: fadd
[all …]
Dfp16-v16-instructions.ll6 ; CHECK-DAG: scvtf [[S0:v[0-9]+\.4s]], v0.4s
7 ; CHECK-DAG: scvtf [[S1:v[0-9]+\.4s]], v1.4s
8 ; CHECK-DAG: scvtf [[S2:v[0-9]+\.4s]], v2.4s
9 ; CHECK-DAG: scvtf [[S3:v[0-9]+\.4s]], v3.4s
10 ; CHECK-DAG: fcvtn v0.4h, [[S0]]
11 ; CHECK-DAG: fcvtn v1.4h, [[S2]]
12 ; CHECK-DAG: v[[R1:[0-9]+]].4h, [[S1]]
13 ; CHECK-DAG: v[[R3:[0-9]+]].4h, [[S3]]
15 ; CHECK-DAG: ins v1.d[1], v[[R3]].d[0]
24 ; CHECK-DAG: scvtf [[D0:v[0-9]+\.2d]], v0.2d
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dfp128-bitcast-after-operation.ll10 ; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]]
11 ; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
12 ; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
13 ; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
14 ; PPC64-DAG: li [[MASK_REG:[0-9]+]], 1
16 ; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
17 ; PPC64-DAG: ld [[LO:[0-9]+]], [[OFFSET_HI]]([[SP]])
19 ; PPC64-DAG: xor 3, [[HI]], [[FLIP_BIT]]
20 ; PPC64-DAG: xor 4, [[LO]], [[FLIP_BIT]]
24 ; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
[all …]
Dvsx-fma-m.ll21 ; CHECK-DAG: li [[C1:[0-9]+]], 8
22 ; CHECK-DAG: xsmaddmdp 3, 2, 1
23 ; CHECK-DAG: xsmaddadp 1, 2, 4
24 ; CHECK-DAG: stxsdx 3, 0, 7
25 ; CHECK-DAG: stxsdx 1, 7, [[C1]]
29 ; CHECK-FISL-DAG: fmr 0, 1
30 ; CHECK-FISL-DAG: xsmaddadp 0, 2, 3
31 ; CHECK-FISL-DAG: stxsdx 0, 0, 7
32 ; CHECK-FISL-DAG: xsmaddadp 1, 2, 4
33 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8
[all …]
Dunal-vec-ldst.ll11 ; CHECK-DAG: li [[REG1:[0-9]+]], 15
12 ; CHECK-DAG: lvsl [[REG2:[0-9]+]], 0, 3
13 ; CHECK-DAG: lvx [[REG3:[0-9]+]], 3, [[REG1]]
14 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 0, 3
25 ; CHECK-DAG: li [[REG1:[0-9]+]], 31
26 ; CHECK-DAG: li [[REG2:[0-9]+]], 16
27 ; CHECK-DAG: lvsl [[REG3:[0-9]+]], 0, 3
28 ; CHECK-DAG: lvx [[REG4:[0-9]+]], 3, [[REG1]]
29 ; CHECK-DAG: lvx [[REG5:[0-9]+]], 3, [[REG2]]
30 ; CHECK-DAG: lvx [[REG6:[0-9]+]], 0, 3
[all …]
Dvsx-fma-sp.ll15 ; CHECK-DAG: li [[C1:[0-9]+]], 4
16 ; CHECK-DAG: xsmaddmsp 3, 2, 1
17 ; CHECK-DAG: xsmaddasp 1, 2, 4
18 ; CHECK-DAG: stxsspx 3, 0, 7
19 ; CHECK-DAG: stxsspx 1, 7, [[C1]]
23 ; CHECK-FISL-DAG: fmr 0, 1
24 ; CHECK-FISL-DAG: xsmaddasp 0, 2, 3
25 ; CHECK-FISL-DAG: stxsspx 0, 0, 7
26 ; CHECK-FISL-DAG: xsmaddasp 1, 2, 4
27 ; CHECK-FISL-DAG: li [[C1:[0-9]+]], 4
[all …]
Dstack-realign.ll32 ; CHECK-DAG: mflr {{[0-9]+}}
33 ; CHECK-DAG: clrldi [[REG:[0-9]+]], 1, 59
34 ; CHECK-DAG: std 30, -16(1)
35 ; CHECK-DAG: mr 30, 1
36 ; CHECK-DAG: std 0, 16(1)
37 ; CHECK-DAG: subfic 0, [[REG]], -160
47 ; CHECK-DAG: ld [[SR:[0-9]+]], 16(1)
48 ; CHECK-DAG: ld 30, -16(1)
49 ; CHECK-DAG: mtlr [[SR]]
54 ; CHECK-FP-DAG: mflr {{[0-9]+}}
[all …]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp655 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn()
656 return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain); in LowerReturn()
666 SelectionDAG &DAG = CLI.DAG; in LowerCall() local
668 const Function &Fn = *DAG.getMachineFunction().getFunction(); in LowerCall()
679 DAG.getContext()->diagnose(NoCalls); in LowerCall()
682 InVals.push_back(DAG.getUNDEF(CLI.Ins[I].VT)); in LowerCall()
684 return DAG.getEntryNode(); in LowerCall()
688 SelectionDAG &DAG) const { in LowerDYNAMIC_STACKALLOC()
689 const Function &Fn = *DAG.getMachineFunction().getFunction(); in LowerDYNAMIC_STACKALLOC()
693 DAG.getContext()->diagnose(NoDynamicAlloca); in LowerDYNAMIC_STACKALLOC()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp61 SelectionDAG &DAG; member in __anoneab193ed0111::SelectionDAGLegalize
71 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
77 SelectionDAGLegalize(SelectionDAG &DAG, in SelectionDAGLegalize() argument
80 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG), in SelectionDAGLegalize()
174 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
175 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
180 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
186 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
187 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
189 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelLowering.cpp166 LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
170 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); in LowerOperation()
171 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
172 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
173 case ISD::BR_JT: return LowerBR_JT(Op, DAG); in LowerOperation()
174 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
175 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
176 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
177 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
[all …]

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