| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyLowerBrUnless.cpp | 75 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction() local
76 switch (Def->getOpcode()) { in runOnMachineFunction()
78 case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break; in runOnMachineFunction()
79 case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break; in runOnMachineFunction()
80 case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break; in runOnMachineFunction()
81 case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break; in runOnMachineFunction()
82 case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break; in runOnMachineFunction()
83 case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break; in runOnMachineFunction()
84 case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break; in runOnMachineFunction()
85 case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break; in runOnMachineFunction()
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| D | WebAssemblyRegStackify.cpp | 219 static bool ShouldRematerialize(const MachineInstr &Def, AliasAnalysis &AA, in ShouldRematerialize() argument
221 return Def.isAsCheapAsAMove() && TII->isTriviallyReMaterializable(Def, &AA); in ShouldRematerialize()
232 if (MachineInstr *Def = MRI.getUniqueVRegDef(Reg)) in GetVRegDef() local
233 return Def; in GetVRegDef()
246 static bool HasOneUse(unsigned Reg, MachineInstr *Def, in HasOneUse() argument
256 LIS.getInstructionIndex(*Def).getRegSlot()); in HasOneUse()
276 static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert, in IsSafeToMove() argument
279 assert(Def->getParent() == Insert->getParent()); in IsSafeToMove()
282 for (const MachineOperand &MO : Def->operands()) { in IsSafeToMove()
312 (MO.isDef() || Def->definesRegister(Reg)) ? in IsSafeToMove()
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| D | WebAssemblyRegisterInfo.cpp | 88 MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg); in eliminateFrameIndex() local
92 if (Def && Def->getOpcode() == WebAssembly::CONST_I32 && in eliminateFrameIndex()
93 MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) { in eliminateFrameIndex()
94 MachineOperand &ImmMO = Def->getOperand(1); in eliminateFrameIndex()
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 294 const MachineInstr *Def; member in __anonc6b70f480111::ValueTracker
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg), in ValueTracker()
357 Def = MRI.getVRegDef(Reg); in ValueTracker()
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg), in ValueTracker()
375 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
376 Def->getOperand(DefIdx).isReg() && "Invalid definition"); in ValueTracker()
377 Reg = Def->getOperand(DefIdx).getReg(); in ValueTracker()
820 TargetInstrInfo::RegSubRegPair Def, in getNewSource() argument
824 TargetInstrInfo::RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
873 RewriteSource(TargetInstrInfo::RegSubRegPair Def, in RewriteSource() argument
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| D | MachineCopyPropagation.cpp | 65 bool eraseIfRedundant(MachineInstr &Copy, unsigned Src, unsigned Def);
130 unsigned Def, const TargetRegisterInfo *TRI) { in isNopCopy() argument
134 assert(Def == PreviousDef); in isNopCopy()
140 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def); in isNopCopy()
147 unsigned Def) { in eraseIfRedundant() argument
150 if (MRI->isReserved(Src) || MRI->isReserved(Def)) in eraseIfRedundant()
154 Reg2MIMap::iterator CI = AvailCopyMap.find(Def); in eraseIfRedundant()
160 if (!isNopCopy(PrevCopy, Src, Def, TRI)) in eraseIfRedundant()
169 assert(CopyDef == Src || CopyDef == Def); in eraseIfRedundant()
188 unsigned Def = MI->getOperand(0).getReg(); in CopyPropagateBlock() local
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| D | DetectDeadLanes.cpp | 93 LaneBitmask transferDefinedLanes(const MachineOperand &Def, unsigned OpNum,
255 const MachineOperand &Def = MI.getOperand(0); in transferUsedLanes() local
256 unsigned DefReg = Def.getReg(); in transferUsedLanes()
290 const MachineOperand &Def = *MI.defs().begin(); in transferDefinedLanesStep() local
291 unsigned DefReg = Def.getReg(); in transferDefinedLanesStep()
301 DefinedLanes = transferDefinedLanes(Def, OpNum, DefinedLanes); in transferDefinedLanesStep()
313 LaneBitmask DetectDeadLanes::transferDefinedLanes(const MachineOperand &Def, in transferDefinedLanes() argument
315 const MachineInstr &MI = *Def.getParent(); in transferDefinedLanes()
349 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
351 DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg()); in transferDefinedLanes()
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| D | LiveVariables.cpp | 199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef() local
200 if (!Def) in FindLastPartialDef()
202 unsigned Dist = DistanceMap[Def]; in FindLastPartialDef()
205 LastDef = Def; in FindLastPartialDef()
292 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastRefOrPartRef() local
293 if (Def && Def != LastDef) { in FindLastRefOrPartRef()
296 unsigned Dist = DistanceMap[Def]; in FindLastRefOrPartRef()
341 MachineInstr *Def = PhysRegDef[SubReg]; in HandlePhysRegKill() local
342 if (Def && Def != LastDef) { in HandlePhysRegKill()
345 unsigned Dist = DistanceMap[Def]; in HandlePhysRegKill()
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| D | LiveInterval.cpp | 62 VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator) { in createDeadDef() argument
63 assert(!Def.isDead() && "Cannot define a value at the dead slot"); in createDeadDef()
65 iterator I = impl().find(Def); in createDeadDef()
67 VNInfo *VNI = LR->getNextValue(Def, VNInfoAllocator); in createDeadDef()
68 impl().insertAtEnd(Segment(Def, Def.getDeadSlot(), VNI)); in createDeadDef()
73 if (SlotIndex::isSameInstr(Def, S->start)) { in createDeadDef()
81 Def = std::min(Def, S->start); in createDeadDef()
82 if (Def != S->start) in createDeadDef()
83 S->start = S->valno->def = Def; in createDeadDef()
86 assert(SlotIndex::isEarlierInstr(Def, S->start) && "Already live at def"); in createDeadDef()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 501 static bool canDefBePartOfLOH(const MachineInstr *Def) { in canDefBePartOfLOH() argument
502 unsigned Opc = Def->getOpcode(); in canDefBePartOfLOH()
511 switch (Def->getOperand(2).getType()) { in canDefBePartOfLOH()
522 switch (Def->getOperand(2).getType()) { in canDefBePartOfLOH()
578 const MachineInstr *Def = DefsIt.first; in reachedUsesToDefs() local
582 if ((ADRPMode && Def->getOpcode() != AArch64::ADRP) || in reachedUsesToDefs()
583 (!ADRPMode && !canDefBePartOfLOH(Def)) || in reachedUsesToDefs()
701 const MachineInstr *Def = *UseToDefs.find(Instr)->second.begin(); in isCandidate() local
702 if (Def->getOpcode() != AArch64::ADRP) { in isCandidate()
709 if (!MDT->dominates(Def, Instr)) in isCandidate()
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| D | AArch64AdvSIMDScalarPass.cpp | 217 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
219 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
220 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in isProfitableToTransform()
230 MachineRegisterInfo::def_instr_iterator Def = in isProfitableToTransform() local
232 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
233 MachineOperand *MOSrc1 = getSrcFromCopy(&*Def, MRI, SubReg1); in isProfitableToTransform()
310 MachineRegisterInfo::def_instr_iterator Def = in transformInstruction() local
312 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
313 MachineOperand *MOSrc0 = getSrcFromCopy(&*Def, MRI, SubReg0); in transformInstruction()
323 Def->eraseFromParent(); in transformInstruction()
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| /external/llvm/lib/IR/ |
| D | Dominators.cpp | 75 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
78 const BasicBlock *DefBB = Def->getParent(); in dominates()
89 if (Def == User) in dominates()
96 if (isa<InvokeInst>(Def) || isa<PHINode>(User)) in dominates()
97 return dominates(Def, UseBB); in dominates()
104 for (; &*I != Def && &*I != User; ++I) in dominates()
107 return &*I == Def; in dominates()
112 bool DominatorTree::dominates(const Instruction *Def, in dominates() argument
114 const BasicBlock *DefBB = Def->getParent(); in dominates()
129 if (const auto *II = dyn_cast<InvokeInst>(Def)) { in dominates()
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| /external/llvm/lib/Target/X86/ |
| D | X86WinAllocaExpander.cpp | 85 MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg); in getWinAllocaAmount() local
88 while (Def && Def->isCopy() && Def->getOperand(1).isReg()) in getWinAllocaAmount()
89 Def = MRI->getUniqueVRegDef(Def->getOperand(1).getReg()); in getWinAllocaAmount()
91 if (!Def || in getWinAllocaAmount()
92 (Def->getOpcode() != X86::MOV32ri && Def->getOpcode() != X86::MOV64ri) || in getWinAllocaAmount()
93 !Def->getOperand(1).isImm()) in getWinAllocaAmount()
96 return Def->getOperand(1).getImm(); in getWinAllocaAmount()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.h | 61 CodeGenSchedRW(unsigned Idx, Record *Def) in CodeGenSchedRW()
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { in CodeGenSchedRW()
63 Name = Def->getName(); in CodeGenSchedRW()
64 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
65 HasVariants = Def->isSubClassOf("SchedVariant"); in CodeGenSchedRW()
67 IsVariadic = Def->getValueAsBit("Variadic"); in CodeGenSchedRW()
72 IsSequence = Def->isSubClassOf("WriteSequence"); in CodeGenSchedRW()
333 CodeGenSchedRW &getSchedRW(Record *Def) { in getSchedRW() argument
334 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW()
335 unsigned Idx = getSchedRWIdx(Def, IsRead); in getSchedRW()
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| /external/clang/test/Index/Core/ |
| D | index-source.m | 11 // CHECK: [[@LINE+1]]:6 | function/C | goo | c:@F@goo | _goo | Def | rel: 0
52 // CHECK: [[@LINE+1]]:6 | enum/C | MyEnum | c:@E@MyEnum | <no-cgname> | Def | rel: 0
54 …merator/C | EnumeratorInNamed | c:@E@MyEnum@EnumeratorInNamed | <no-cgname> | Def,RelChild | rel: 1
59 // CHECK: [[@LINE+1]]:1 | enum/C | <no-name> | c:@Ea@One | <no-cgname> | Def | rel: 0
61 // CHECK: [[@LINE+2]]:3 | enumerator/C | One | c:@Ea@One@One | <no-cgname> | Def,RelChild | rel: 1
64 // CHECK: [[@LINE+2]]:3 | enumerator/C | Two | c:@Ea@One@Two | <no-cgname> | Def,RelChild | rel: 1
69 // CHECK: [[@LINE+1]]:13 | type-alias/C | jmp_buf | c:index-source.m@T@jmp_buf | <no-cgname> | Def …
85 // CHECK: [[@LINE+2]]:17 | field/ObjC | _prop | c:objc(cs)I2@_prop | <no-cgname> | Def,Impl,RelChil…
89 // CHECK: [[@LINE+4]]:13 | instance-method/ObjC | prop | c:objc(cs)I2(im)prop | -[I2 prop] | Def,Re…
91 …instance-method/ObjC | setProp: | c:objc(cs)I2(im)setProp: | -[I2 setProp:] | Def,RelChild | rel: 1
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| D | index-subkinds.m | 10 // CHECK: [[@LINE+1]]:17 | class(test)/ObjC | MyTestCase | c:objc(cs)MyTestCase | <no-cgname> | Def…
12 …t)/ObjC | testMe | c:objc(cs)MyTestCase(im)testMe | -[MyTestCase testMe] | Def,Dyn,RelChild | rel:…
14 …stResult | c:objc(cs)MyTestCase(im)testResult | -[MyTestCase testResult] | Def,Dyn,RelChild | rel:…
16 …Int: | c:objc(cs)MyTestCase(im)testWithInt: | -[MyTestCase testWithInt:] | Def,Dyn,RelChild | rel:…
23 …[@LINE+1]]:17 | class(test)/ObjC | SubTestCase | c:objc(cs)SubTestCase | <no-cgname> | Def | rel: 0
25 …jC | testIt2 | c:objc(cs)SubTestCase(im)testIt2 | -[SubTestCase testIt2] | Def,Dyn,RelChild | rel:…
32 …[@LINE+1]]:17 | extension/ObjC | MyTestCase | c:objc(cy)MyTestCase@cat | <no-cgname> | Def | rel: 0
34 …InCat | c:objc(cs)MyTestCase(im)testInCat | -[MyTestCase(cat) testInCat] | Def,Dyn,RelChild | rel:…
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| /external/clang/lib/Lex/ |
| D | MacroInfo.cpp | 202 for (DefInfo Def = getDefinition(); Def; Def = Def.getPreviousDefinition()) { in findDirectiveAtLoc() local
203 if (Def.getLocation().isInvalid() || // For macros defined on the command line. in findDirectiveAtLoc()
204 SM.isBeforeInTranslationUnit(Def.getLocation(), L)) in findDirectiveAtLoc()
205 return (!Def.isUndefined() || in findDirectiveAtLoc()
206 SM.isBeforeInTranslationUnit(L, Def.getUndefLocation())) in findDirectiveAtLoc()
207 ? Def : DefInfo(); in findDirectiveAtLoc()
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| /external/lzma/CPP/Common/ |
| D | MyTypes.h | 13 bool Def; member
15 CBoolPair(): Val(false), Def(false) {} in CBoolPair()
20 Def = false; in Init()
26 Def = true; in SetTrueTrue()
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 206 MachineInstr *Def = Op->getParent(); in eraseInstrWithNoUses() local
210 if (DeadInstr.find(Def) != DeadInstr.end()) in eraseInstrWithNoUses()
217 for (unsigned int j = 0; j < Def->getNumOperands(); ++j) { in eraseInstrWithNoUses()
218 MachineOperand &MODef = Def->getOperand(j); in eraseInstrWithNoUses()
230 if (&*II == Def) in eraseInstrWithNoUses()
241 DEBUG(dbgs() << "Deleting instruction " << *Def << "\n"); in eraseInstrWithNoUses()
242 DeadInstr.insert(Def); in eraseInstrWithNoUses()
311 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern() local
312 if (!Def) in optimizeSDPattern()
314 if (Def->isImplicitDef()) in optimizeSDPattern()
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| /external/clang/test/Modules/ |
| D | decldef.mm | 11 @class Def;
12 Def *def;
24 A *a1; // expected-error{{declaration of 'A' must be imported from module 'decldef.Def'}}
37 …// expected-error@-2{{definition of 'A' must be imported from module 'decldef.Def' before it is re…
47 …// expected-error@-2{{definition of 'B' must be imported from module 'decldef.Def' before it is re…
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| D | decldef.m | 7 @class Def;
8 Def *def;
12 A *a1; // expected-error{{declaration of 'A' must be imported from module 'decldef.Def' before it i…
29 …// expected-error@-2{{definition of 'A' must be imported from module 'decldef.Def' before it is re…
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| /external/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 1973 for (auto *Def : Defs) { in genBuiltinsDef() local
1974 if (Def->hasBody()) in genBuiltinsDef()
1978 if (Def->hasSplat()) in genBuiltinsDef()
1981 std::string S = "BUILTIN(__builtin_neon_" + Def->getMangledName() + ", \""; in genBuiltinsDef()
1983 S += Def->getBuiltinTypeStr(); in genBuiltinsDef()
2011 for (auto *Def : Defs) { in genOverloadTypeCheckCode() local
2014 if (Def->hasBody()) in genOverloadTypeCheckCode()
2018 if (Def->hasSplat()) in genOverloadTypeCheckCode()
2022 if (Def->protoHasScalar()) in genOverloadTypeCheckCode()
2026 Type Ty = Def->getReturnType(); in genOverloadTypeCheckCode()
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| /external/lzma/CPP/7zip/UI/Console/ |
| D | List.cpp | 299 bool Def; member
301 CListUInt64Def(): Val(0), Def(false) {} in CListUInt64Def()
302 void Add(UInt64 v) { Val += v; Def = true; } in Add()
303 void Add(const CListUInt64Def &v) { if (v.Def) Add(v.Val); } in Add()
309 bool Def; member
311 CListFileTimeDef(): Def(false) { Val.dwLowDateTime = 0; Val.dwHighDateTime = 0; } in CListFileTimeDef()
314 if (t.Def && (!Def || CompareFileTime(&Val, &t.Val) < 0)) in Update()
317 Def = true; in Update()
337 void SetSizeDefIfNoFiles() { if (NumFiles == 0) Size.Def = true; } in SetSizeDefIfNoFiles()
636 case kpidSize: if (st.Size.Def) prop = st.Size.Val; break; in PrintItemInfo()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | LiveVariables.cpp | 195 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef() local
196 if (!Def) in FindLastPartialDef()
198 unsigned Dist = DistanceMap[Def]; in FindLastPartialDef()
201 LastDef = Def; in FindLastPartialDef()
291 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastRefOrPartRef() local
292 if (Def && Def != LastDef) { in FindLastRefOrPartRef()
295 unsigned Dist = DistanceMap[Def]; in FindLastRefOrPartRef()
340 MachineInstr *Def = PhysRegDef[SubReg]; in HandlePhysRegKill() local
341 if (Def && Def != LastDef) { in HandlePhysRegKill()
344 unsigned Dist = DistanceMap[Def]; in HandlePhysRegKill()
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 164 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) { in expand()
165 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices"); in expand()
167 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); in expand()
169 throw TGError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch"); in expand()
171 throw TGError(Def->getLoc(), "Tuples must have at least 2 sub-registers"); in expand()
185 Record *RegisterCl = Def->getRecords().getClass("Register"); in expand()
207 Record *NewReg = new Record(Name, Def->getLoc(), Def->getRecords()); in expand()
233 NewReg->addValue(*Def->getValue(RV.getName())); in expand()
564 CodeGenRegister *CodeGenRegBank::getReg(Record *Def) { in getReg() argument
565 CodeGenRegister *&Reg = Def2Reg[Def]; in getReg()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.cpp | 185 … NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), in init()
197 … NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), in init()
562 const NewSense &Def = Defs[i]; in hasValidNewValueDef() local
564 if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0)) in hasValidNewValueDef()
568 if (Def.PredReg == 0) in hasValidNewValueDef()
573 if (Def.PredReg == Use.PredReg && Def.Cond == Use.Cond) in hasValidNewValueDef()
579 if (Def.PredReg != Use.PredReg || Def.Cond == Use.Cond) in hasValidNewValueDef()
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