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Searched refs:EDX (Results 1 – 25 of 127) sorted by relevance

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/external/mesa3d/src/mesa/x86/
D3dnow_xform3.S48 MOV_L ( REGOFF(V4F_COUNT, EAX), EDX )
49 MOV_L ( EDX, REGOFF(V4F_COUNT, ECX) )
53 MOV_L ( REGOFF(V4F_START, ECX), EDX )
62 PREFETCHW ( REGIND(EDX) )
67 PREFETCHW ( REGOFF(32, EDX) ) /* prefetch 2 vertices ahead */
100 ADD_L ( CONST(16), EDX ) /* next output vertex */
103 MOVQ ( MM2, REGOFF(-16, EDX) ) /* write r0, r1 */
106 MOVQ ( MM5, REGOFF(-8, EDX) ) /* write r2, r3 */
133 MOV_L ( REGOFF(V4F_COUNT, EAX), EDX )
134 MOV_L ( EDX, REGOFF(V4F_COUNT, ECX) )
[all …]
D3dnow_xform4.S48 MOV_L ( REGOFF(V4F_COUNT, EAX), EDX )
49 MOV_L ( EDX, REGOFF(V4F_COUNT, ECX) )
53 MOV_L ( REGOFF(V4F_START, ECX), EDX )
62 PREFETCHW ( REGIND(EDX) )
67 PREFETCHW ( REGOFF(32, EDX) ) /* prefetch 2 vertices ahead */
82 ADD_L ( CONST(16), EDX ) /* next r */
112 MOVQ ( MM6, REGOFF(-16, EDX) )
114 MOVQ ( MM7, REGOFF(-8, EDX) )
141 MOV_L ( REGOFF(V4F_COUNT, EAX), EDX )
142 MOV_L ( EDX, REGOFF(V4F_COUNT, ECX) )
[all …]
D3dnow_xform1.S48 MOV_L ( REGOFF(V4F_COUNT, EAX), EDX )
49 MOV_L ( EDX, REGOFF(V4F_COUNT, ECX) )
53 MOV_L ( REGOFF(4, ECX), EDX )
81 MOVQ ( MM4, REGIND(EDX) ) /* write r1, r0 */
83 MOVQ ( MM5, REGOFF(8, EDX) ) /* write r3, r2 */
86 ADD_L ( CONST(16), EDX ) /* next r */
113 MOV_L ( REGOFF(V4F_COUNT, EAX), EDX )
114 MOV_L ( EDX, REGOFF(V4F_COUNT, ECX) )
118 MOV_L ( REGOFF(4, ECX), EDX )
133 MOVD ( MM0, REGIND(EDX) ) /* | r0 */
[all …]
D3dnow_xform2.S48 MOV_L ( REGOFF(V4F_COUNT, EAX), EDX )
49 MOV_L ( EDX, REGOFF(V4F_COUNT, ECX) )
53 MOV_L ( REGOFF(V4F_START, ECX), EDX )
89 MOVQ ( MM6, REGIND(EDX) ) /* write r1, r0 */
101 MOVQ ( MM6, REGOFF(8, EDX) ) /* write r3, r2 */
102 ADD_L ( CONST(16), EDX ) /* next r */
129 MOV_L ( REGOFF(V4F_COUNT, EAX), EDX )
130 MOV_L ( EDX, REGOFF(V4F_COUNT, ECX) )
134 MOV_L ( REGOFF(V4F_START, ECX), EDX )
154 MOVQ ( MM4, REGIND(EDX) ) /* write r1, r0 */
[all …]
Dx86_cliptest.S44 #define MAT0 REGOFF(0, EDX)
45 #define MAT1 REGOFF(4, EDX)
46 #define MAT2 REGOFF(8, EDX)
47 #define MAT3 REGOFF(12, EDX)
136 MOV_L( ARG_CLIP, EDX )
152 ADD_L( EDX, ECX )
155 CMP_L( ECX, EDX )
210 MOV_B( CL, REGIND(EDX) )
244 INC_L( EDX )
248 CMP_L( EDX, ARG_CLIP )
[all …]
Dx86_xform2.S49 #define MAT0 REGOFF(0, EDX)
50 #define MAT1 REGOFF(4, EDX)
51 #define MAT2 REGOFF(8, EDX)
52 #define MAT3 REGOFF(12, EDX)
53 #define MAT4 REGOFF(16, EDX)
54 #define MAT5 REGOFF(20, EDX)
55 #define MAT6 REGOFF(24, EDX)
56 #define MAT7 REGOFF(28, EDX)
57 #define MAT8 REGOFF(32, EDX)
58 #define MAT9 REGOFF(36, EDX)
[all …]
Dx86_xform3.S49 #define MAT0 REGOFF(0, EDX)
50 #define MAT1 REGOFF(4, EDX)
51 #define MAT2 REGOFF(8, EDX)
52 #define MAT3 REGOFF(12, EDX)
53 #define MAT4 REGOFF(16, EDX)
54 #define MAT5 REGOFF(20, EDX)
55 #define MAT6 REGOFF(24, EDX)
56 #define MAT7 REGOFF(28, EDX)
57 #define MAT8 REGOFF(32, EDX)
58 #define MAT9 REGOFF(36, EDX)
[all …]
Dx86_xform4.S49 #define MAT0 REGOFF(0, EDX)
50 #define MAT1 REGOFF(4, EDX)
51 #define MAT2 REGOFF(8, EDX)
52 #define MAT3 REGOFF(12, EDX)
53 #define MAT4 REGOFF(16, EDX)
54 #define MAT5 REGOFF(20, EDX)
55 #define MAT6 REGOFF(24, EDX)
56 #define MAT7 REGOFF(28, EDX)
57 #define MAT8 REGOFF(32, EDX)
58 #define MAT9 REGOFF(36, EDX)
[all …]
Dsse_normal.S40 #define M(i) REGOFF(i * 4, EDX)
58 MOV_L ( ARG_MAT, EDX ) /* ptr to matrix */
59 MOV_L ( REGOFF(MATRIX_INV, EDX), EDX) /* matrix->inv */
120 MOV_L ( ARG_MAT, EDX ) /* ptr to matrix */
121 MOV_L ( REGOFF(MATRIX_INV, EDX), EDX) /* matrix->inv */
213 MOV_L ( ARG_MAT, EDX ) /* ptr to matrix */
214 MOV_L ( REGOFF(MATRIX_INV, EDX), EDX) /* matrix->inv */
Dsse_xform2.S42 #define M(i) REGOFF(i * 4, EDX)
57 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
141 MOV_L ( S(0), EDX )
142 MOV_L ( EDX, D(0) )
143 MOV_L ( S(1), EDX )
144 MOV_L ( EDX, D(1) )
171 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
232 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
291 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
354 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
[all …]
Dsse_xform3.S42 #define M(i) REGOFF(i * 4, EDX)
57 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
77 MOVAPS ( REGOFF(0, EDX), XMM0 ) /* m0 | m1 | m2 | m3 */
78 MOVAPS ( REGOFF(16, EDX), XMM1 ) /* m4 | m5 | m6 | m7 */
79 MOVAPS ( REGOFF(32, EDX), XMM2 ) /* m8 | m9 | m10 | m11 */
80 MOVAPS ( REGOFF(48, EDX), XMM3 ) /* m12 | m13 | m14 | m15 */
183 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
250 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
323 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
388 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
[all …]
Dsse_xform1.S42 #define M(i) REGOFF(i * 4, EDX)
57 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
137 MOV_L( S(0), EDX )
138 MOV_L( EDX, D(0) )
166 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
227 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
286 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
341 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
398 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
Dsse_xform4.S37 #define MAT(i) REGOFF(i * 4, EDX)
53 MOV_L( ARG_MATRIX, EDX )
125 MOV_L( ARG_MATRIX, EDX ) /* ptr to matrix */
197 MOV_L( ARG_MATRIX, EDX )
/external/llvm/lib/Support/
DHost.cpp706 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, in getAvailableFeatures() argument
710 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); in getAvailableFeatures()
711 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); in getAvailableFeatures()
712 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); in getAvailableFeatures()
723 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && in getAvailableFeatures()
727 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); in getAvailableFeatures()
737 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in getAvailableFeatures()
738 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); in getAvailableFeatures()
743 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in getHostCPUName() local
746 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) in getHostCPUName()
[all …]
/external/swiftshader/third_party/llvm-subzero/lib/Support/
DHost.cpp740 static unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX, in getAvailableFeatures() argument
744 Features |= (((EDX >> 23) & 1) << FEATURE_MMX); in getAvailableFeatures()
745 Features |= (((EDX >> 25) & 1) << FEATURE_SSE); in getAvailableFeatures()
746 Features |= (((EDX >> 26) & 1) << FEATURE_SSE2); in getAvailableFeatures()
757 bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) && in getAvailableFeatures()
761 MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX); in getAvailableFeatures()
771 getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in getAvailableFeatures()
772 Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T); in getAvailableFeatures()
777 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in getHostCPUName() local
788 if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX)) in getHostCPUName()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86Subtarget.cpp179 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in AutoDetectSubtargetFeatures() local
188 X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); in AutoDetectSubtargetFeatures()
190 if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); } in AutoDetectSubtargetFeatures()
191 if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); } in AutoDetectSubtargetFeatures()
192 if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); } in AutoDetectSubtargetFeatures()
193 if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); } in AutoDetectSubtargetFeatures()
253 X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in AutoDetectSubtargetFeatures()
254 if ((EDX >> 29) & 0x1) { in AutoDetectSubtargetFeatures()
/external/lzma/C/
DCpuArch.c24 __asm mov EDX, EAX; in CheckFlag() local
30 __asm xor EAX, EDX; in CheckFlag() local
31 __asm push EDX; in CheckFlag() local
67 __asm xor EDX, EDX; in MyCPUID() local
73 __asm mov d2, EDX; in MyCPUID() local
/external/swiftshader/third_party/LLVM/lib/Support/
DHost.cpp109 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; in getHostCPUName() local
110 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX)) in getHostCPUName()
117 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); in getHostCPUName()
118 bool Em64T = (EDX >> 29) & 0x1; in getHostCPUName()
/external/llvm/test/CodeGen/X86/
Dhandle-move.ll8 ; %EDX has a live range into the function and is used by the DIV32r.
11 …4B -> 180B: DIV32r %vreg4, %EAX<imp-def>, %EDX<imp-def,dead>, %EFLAGS<imp-def,dead>, %EAX<imp-use,…
28 … -> 180B: DIV32r %vreg4, %EAX<imp-def,dead>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use,ki…
62 ; handleMove 208B -> 36B: %EDX<def> = MOV32r0 %EFLAGS<imp-def,dead>
Dpromote-vec3.ll24 ; SSE3-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
38 ; SSE41-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
52 ; AVX_ANY-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
66 ; AVX_X86_64-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
90 ; SSE3-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
105 ; SSE41-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
120 ; AVX_ANY-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
135 ; AVX_X86_64-NEXT: # kill: %DX<def> %DX<kill> %EDX<kill>
Dinline-asm-tied.ll4 ; CHECK: movl [[EDX:%e..]], 4(%esp)
5 ; CHECK: movl [[EDX]], 4(%esp)
Dabi-isel.ll1684 ; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[EDX:%e.x]]
1685 ; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
1693 ; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L24$pb([[EAX]]), [[EDX:%e.x]]
1694 ; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]]
1696 ; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4)
1762 ; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[EDX:%e.x]]
1763 ; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
1771 ; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L25$pb([[EAX]]), [[EDX:%e.x]]
1772 ; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]]
1774 ; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4)
[all …]
/external/llvm/lib/Target/X86/
DX86InstrSystem.td439 let Uses = [EAX, ECX, EDX] in
441 let Defs = [EAX, EDX], Uses = [ECX] in
465 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
480 let Defs = [EDX, EAX], Uses = [ECX] in
483 let Uses = [EDX, EAX, ECX] in
487 let Uses = [EDX, EAX] in {
491 [(int_x86_xsave addr:$dst, EDX, EAX)]>, TB;
494 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
497 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, TB;
500 [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
[all …]
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp80 X86::EDX, X86::EBX, X86::ESP, X86::EBP, X86::ESI, X86::EDI, in initLLVMToSEHAndCVRegMapping()
295 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
307 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
344 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
380 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
381 return X86::EDX; in getX86SubSuperRegisterOrZero()
416 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: in getX86SubSuperRegisterOrZero()
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dabi-isel.ll1684 ; DARWIN-32-DYNAMIC-NEXT: movl L_dst$non_lazy_ptr, [[EDX:%e.x]]
1685 ; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
1693 ; DARWIN-32-PIC-NEXT: movl L_src$non_lazy_ptr-L24$pb([[EAX]]), [[EDX:%e.x]]
1694 ; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]]
1696 ; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4)
1762 ; DARWIN-32-DYNAMIC-NEXT: movl L_xdst$non_lazy_ptr, [[EDX:%e.x]]
1763 ; DARWIN-32-DYNAMIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
1771 ; DARWIN-32-PIC-NEXT: movl L_xsrc$non_lazy_ptr-L25$pb([[EAX]]), [[EDX:%e.x]]
1772 ; DARWIN-32-PIC-NEXT: movl ([[EDX]],[[ECX]],4), [[EDX:%e.x]]
1774 ; DARWIN-32-PIC-NEXT: movl [[EDX]], ([[EAX]],[[ECX]],4)
[all …]

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