| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 54 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
426 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
613 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
615 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
755 LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), in SplitVecRes_SETCC()
757 LH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), in SplitVecRes_SETCC()
760 RL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), in SplitVecRes_SETCC()
762 RH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(1), in SplitVecRes_SETCC()
783 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), in SplitVecRes_UnaryOp()
785 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), in SplitVecRes_UnaryOp()
[all …]
|
| D | LegalizeTypesGeneric.cpp | 85 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, in ExpandRes_BITCAST()
87 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, in ExpandRes_BITCAST()
454 CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond, in SplitRes_SELECT()
456 CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond, in SplitRes_SELECT()
|
| D | LegalizeIntegerTypes.cpp | 79 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
593 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp, in PromoteIntRes_TRUNCATE()
595 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp, in PromoteIntRes_TRUNCATE()
|
| D | SelectionDAGBuilder.cpp | 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, in getCopyFromPartsVector()
513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, in getCopyToPartsVector()
2916 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, in visitShuffleVector()
|
| D | SelectionDAG.cpp | 2928 case ISD::EXTRACT_SUBVECTOR: { in getNode()
6012 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
597 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
838 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
840 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
1461 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break; in SplitVectorOperand()
1607 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx); in SplitVecOp_EXTRACT_SUBVECTOR()
1609 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
2062 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break; in WidenVectorResult()
2243 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1, in WidenVecRes_BinaryCanTrap()
2246 ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2, in WidenVecRes_BinaryCanTrap()
[all …]
|
| D | SelectionDAGDumper.cpp | 222 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 92 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
916 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
3412 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
|
| D | DAGCombiner.cpp | 1434 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
11519 StoredVal.getOpcode() == ISD::EXTRACT_SUBVECTOR); in MergeConsecutiveStores()
11681 StoreValOpcode != ISD::EXTRACT_SUBVECTOR) in MergeConsecutiveStores()
12864 ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1, in visitBUILD_VECTOR()
12868 ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1, in visitBUILD_VECTOR()
12982 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
13159 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
13242 ISD::EXTRACT_SUBVECTOR, dl, NVT, in visitEXTRACT_SUBVECTOR()
|
| D | SelectionDAG.cpp | 3754 case ISD::EXTRACT_SUBVECTOR: in getNode()
7083 Lo = getNode(ISD::EXTRACT_SUBVECTOR, DL, LoVT, N, in SplitVector()
7085 Hi = getNode(ISD::EXTRACT_SUBVECTOR, DL, HiVT, N, in SplitVector()
|
| D | SelectionDAGBuilder.cpp | 340 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, in getCopyFromPartsVector()
589 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, in getCopyToPartsVector()
3147 ISD::EXTRACT_SUBVECTOR, dl, VT, Src, in visitShuffleVector()
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 283 EXTRACT_SUBVECTOR, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 299 EXTRACT_SUBVECTOR, enumerator
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 269 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
270 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
271 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
272 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
273 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom); in AMDGPUTargetLowering()
274 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom); in AMDGPUTargetLowering()
708 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
|
| D | SIISelLowering.cpp | 149 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 669 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForNEON()
2373 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
5035 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5041 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5046 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5049 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5389 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, in tryFormConcatFromShuffle()
5393 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, in tryFormConcatFromShuffle()
5615 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in LowerVECTOR_SHUFFLE()
8001 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR && in performBitcastCombine()
[all …]
|
| /external/llvm/test/CodeGen/X86/ |
| D | vec_extract-avx.ll | 7 ; an EXTRACT_SUBVECTOR node internally rather than a bunch of
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 661 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1099 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1389 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1392 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in X86TargetLowering()
4161 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4444 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in extractSubVector()
4598 return (WideOpVT == OpVT) ? V : DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, in insert1BitVector()
6041 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, in LowerBUILD_VECTORvXi1()
6088 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, in LowerBUILD_VECTORvXi1()
8668 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtVT, V, in lowerVectorShuffleAsBroadcast()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal); in addTypeForNEON()
4130 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
4136 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
4142 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
4145 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, in ReconstructShuffle()
4775 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
4777 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
4779 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
4781 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
4810 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 117 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
4446 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
4731 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended, in lowerCTPOP16BitElements()
4734 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8, in lowerCTPOP16BitElements()
4773 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended, in lowerCTPOP32BitElements()
4776 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2, in lowerCTPOP32BitElements()
5968 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5974 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5979 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5982 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
[all …]
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 465 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
470 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 559 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
564 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1955 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1981 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
2773 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXVector.td | 867 def extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, in Extract128BitVector()
702 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); in X86TargetLowering()
1062 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); in X86TargetLowering()
10399 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
|