/external/v8/src/arm64/ |
D | macro-assembler-arm64.cc | 1545 Eor(scratch2, scratch1, scratch2); in TestJSArrayForAllocationMemento() 1551 Eor(scratch2, scratch1, receiver); in TestJSArrayForAllocationMemento() 3520 Eor(key, key, Operand::UntagSmi(scratch)); in GetNumberHash() 3533 Eor(key, key, Operand(key, LSR, 12)); in GetNumberHash() 3537 Eor(key, key, Operand(key, LSR, 4)); in GetNumberHash() 3543 Eor(key, key, Operand(key, LSR, 16)); in GetNumberHash()
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D | macro-assembler-arm64-inl.h | 107 void MacroAssembler::Eor(const Register& rd, in Eor() function
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D | macro-assembler-arm64.h | 192 inline void Eor(const Register& rd,
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D | code-stubs-arm64.cc | 1517 __ Eor(string_encoding, string_encoding, 1); in Generate()
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/external/vixl/test/aarch32/ |
D | test-disasm-a32.cc | 3335 COMPARE_T32(Eor(eq, r0, r0, r7), in TEST() 3339 COMPARE_T32(Eor(eq, r0, r0, 0x1), in TEST() 4043 CHECK_T32_16(Eor(DontCare, r7, r7, r6), "eors r7, r6\n"); in TEST() 4045 CHECK_T32_16_IT_BLOCK(Eor(DontCare, eq, r7, r7, r6), in TEST()
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D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 124 M(Eor) \
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D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 124 M(Eor) \
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D | test-simulator-cond-rd-rn-operand-const-a32.cc | 124 M(Eor) \
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D | test-simulator-cond-rd-rn-operand-const-t32.cc | 124 M(Eor) \
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D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 124 M(Eor) \
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D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 124 M(Eor) \
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D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 124 M(Eor) \
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D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 124 M(Eor) \
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D | test-assembler-aarch32.cc | 3266 __ Eor(r0, r0, 0); in TEST() local 3310 __ Eor(r3, r0, 0xffffffff); in TEST() local 6050 CHECK_SIZE_MATCH(Eor(r7, r7, r6), Eor(r7, r6, r7)); in TEST_T32()
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D | test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 124 M(Eor) \
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/external/vixl/test/aarch64/ |
D | test-assembler-aarch64.cc | 322 __ Eor(x11, x0, 0x18001); in TEST() local 774 __ Eor(w13, w0, kWMinInt); in TEST() local 1127 __ Eor(x2, x0, Operand(x1)); in TEST() local 1128 __ Eor(w3, w0, Operand(w1, LSL, 4)); in TEST() local 1129 __ Eor(x4, x0, Operand(x1, LSL, 4)); in TEST() local 1130 __ Eor(x5, x0, Operand(x1, LSR, 1)); in TEST() local 1131 __ Eor(w6, w0, Operand(w1, ASR, 20)); in TEST() local 1132 __ Eor(x7, x0, Operand(x1, ASR, 20)); in TEST() local 1133 __ Eor(w8, w0, Operand(w1, ROR, 28)); in TEST() local 1134 __ Eor(x9, x0, Operand(x1, ROR, 28)); in TEST() local [all …]
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D | test-disasm-aarch64.cc | 2988 COMPARE_MACRO(Eor(w4, w5, 0), "mov w4, w5"); in TEST() 2989 COMPARE_MACRO(Eor(x4, x5, 0), "mov x4, x5"); in TEST() 3004 COMPARE_MACRO(Eor(w16, w17, 0xffffffff), "mvn w16, w17"); in TEST() 3005 COMPARE_MACRO(Eor(x16, x17, 0xffffffff), "eor x16, x17, #0xffffffff"); in TEST() 3006 COMPARE_MACRO(Eor(x16, x17, 0xffffffffffffffff), "mvn x16, x17"); in TEST() 4526 COMPARE_MACRO(Eor(v6.V8B(), v7.V8B(), v8.V8B()), "eor v6.8b, v7.8b, v8.8b"); in TEST() 4527 COMPARE_MACRO(Eor(v6.V16B(), v7.V16B(), v8.V16B()), in TEST()
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/external/swiftshader/third_party/subzero/src/ |
D | IceInstARM32.h | 392 Eor, enumerator 1008 using InstARM32Eor = InstARM32ThreeAddrGPR<InstARM32::Eor>;
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D | IceInstARM32.cpp | 3488 template class InstARM32ThreeAddrGPR<InstARM32::Eor>;
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/external/v8/src/compiler/arm64/ |
D | code-generator-arm64.cc | 1087 __ Eor(i.OutputRegister(), i.InputOrZeroRegister64(0), in AssembleArchInstruction() local 1091 __ Eor(i.OutputRegister32(), i.InputOrZeroRegister32(0), in AssembleArchInstruction() local
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/external/v8/src/crankshaft/arm64/ |
D | lithium-codegen-arm64.cc | 1704 case Token::BIT_XOR: __ Eor(result, left, right); break; in DoBitI() local 1720 case Token::BIT_XOR: __ Eor(result, left, right); break; in DoBitS() local 3204 __ Eor(scratch, scratch, kHoleNanInt64); in DoLoadKeyedFixedDouble() local 3622 __ Eor(remainder, dividend, divisor); in DoFlooringDivI() local
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/external/v8/src/full-codegen/arm64/ |
D | full-codegen-arm64.cc | 1567 __ Eor(x11, left, right); in EmitInlineSmiBinaryOp() local 1586 __ Eor(result, left, right); in EmitInlineSmiBinaryOp() local
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/external/vixl/src/aarch64/ |
D | macro-assembler-aarch64.h | 654 void Eor(const Register& rd, const Register& rn, const Operand& operand); 2174 V(eor, Eor) \
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D | macro-assembler-aarch64.cc | 784 void MacroAssembler::Eor(const Register& rd, in Eor() function in vixl::aarch64::MacroAssembler
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/external/vixl/src/aarch32/ |
D | macro-assembler-aarch32.h | 1691 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) { in Eor() function 1715 void Eor(Register rd, Register rn, const Operand& operand) { in Eor() function 1716 Eor(al, rd, rn, operand); in Eor() 1718 void Eor(FlagsUpdate flags, in Eor() function 1725 Eor(cond, rd, rn, operand); in Eor() 1737 Eor(cond, rd, rn, operand); in Eor() 1742 void Eor(FlagsUpdate flags, in Eor() function 1746 Eor(flags, al, rd, rn, operand); in Eor()
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