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Searched refs:ExtType (Results 1 – 25 of 39) sorted by relevance

12

/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.h50 struct ExtType { struct
54 ExtType() : Type(0), Width(0) {} in ExtType() function
55 ExtType(char t, uint16_t w) : Type(t), Width(w) {} in ExtType() function
58 typedef DenseMap<unsigned, ExtType> RegExtMap;
DHexagonISelDAGToDAG.cpp250 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
251 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD); in SelectIndexedLoad()
304 auto getExt64 = [this,ExtType] (MachineSDNode *N, const SDLoc &dl) in SelectIndexedLoad()
306 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) { in SelectIndexedLoad()
311 if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
322 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
DHexagonBitTracker.cpp71 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::SExt, Width))); in HexagonEvaluator()
73 VRX.insert(std::make_pair(InVirtReg, ExtType(ExtType::ZExt, Width))); in HexagonEvaluator()
1120 if (F->second.Type == ExtType::SExt) in evaluateFormalCopy()
1122 else if (F->second.Type == ExtType::ZExt) in evaluateFormalCopy()
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTargetLowering.h397 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const { in getLoadExtAction() argument
398 assert(ExtType < ISD::LAST_LOADEXT_TYPE && in getLoadExtAction()
401 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType]; in getLoadExtAction()
406 bool isLoadExtLegal(unsigned ExtType, EVT VT) const { in isLoadExtLegal() argument
407 return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal; in isLoadExtLegal()
1063 void setLoadExtAction(unsigned ExtType, MVT VT, in setLoadExtAction() argument
1065 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE && in setLoadExtAction()
1067 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action; in setLoadExtAction()
/external/llvm/include/llvm/Target/
DTargetLowering.h657 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, in getLoadExtAction() argument
662 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
664 unsigned Shift = 4 * ExtType; in getLoadExtAction()
669 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
670 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
675 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegalOrCustom() argument
676 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal || in isLoadExtLegalOrCustom()
677 getLoadExtAction(ExtType, ValVT, MemVT) == Custom; in isLoadExtLegalOrCustom()
1433 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
1435 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
[all …]
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1098 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
1104 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1108 ExtType == AArch64_AM::UXTX) || in printArithExtend()
1110 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
1116 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/external/capstone/arch/AArch64/
DAArch64InstPrinter.c809 AArch64_AM_ShiftExtendType ExtType = AArch64_AM_getArithExtendType(Val); in printArithExtend() local
815 if (ExtType == AArch64_AM_UXTW || ExtType == AArch64_AM_UXTX) { in printArithExtend()
819 ExtType == AArch64_AM_UXTX) || in printArithExtend()
821 ExtType == AArch64_AM_UXTW) ) { in printArithExtend()
835 SStream_concat(O, ", %s", AArch64_AM_getShiftExtendName(ExtType)); in printArithExtend()
838 switch(ExtType) { in printArithExtend()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp204 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
205 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
513 ISD::LoadExtType ExtType = LD->getExtensionType(); in ExpandLoad() local
602 switch (ExtType) { in ExpandLoad()
DLegalizeVectorTypes.cpp1049 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
1063 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1070 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1096 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD() local
1127 ExtType); in SplitVecRes_MLOAD()
1139 ExtType); in SplitVecRes_MLOAD()
2839 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
2843 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
2844 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
2870 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_MLOAD() local
[all …]
DLegalizeDAG.cpp625 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeLoadOps() local
626 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeLoadOps()
693 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) == in LegalizeLoadOps()
705 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
715 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
720 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
756 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
778 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
811 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0), in LegalizeLoadOps()
846 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
[all …]
DLegalizeIntegerTypes.cpp478 ISD::LoadExtType ExtType = in PromoteIntRes_LOAD() local
481 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), in PromoteIntRes_LOAD()
2053 ISD::LoadExtType ExtType = N->getExtensionType(); in ExpandIntRes_LOAD() local
2066 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
2073 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
2080 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
2084 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
2102 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
2120 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
2149 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT, in ExpandIntRes_LOAD()
DSelectionDAG.cpp233 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType() argument
234 switch (ExtType) { in getExtForLoadExtType()
2731 unsigned ExtType = LD->getExtensionType(); in ComputeNumSignBits() local
2732 switch (ExtType) { in ComputeNumSignBits()
5052 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
5081 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO); in getLoad()
5084 SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
5089 ExtType = ISD::NON_EXTLOAD; in getLoad()
5090 } else if (ExtType == ISD::NON_EXTLOAD) { in getLoad()
5114 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile(), in getLoad()
[all …]
DDAGCombiner.cpp217 ISD::NodeType ExtType);
960 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteOperand() local
965 return DAG.getExtLoad(ExtType, dl, PVT, in PromoteOperand()
1185 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteLoad() local
1189 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, in PromoteLoad()
5899 const SDLoc &DL, ISD::NodeType ExtType) { in ExtendSetCCUses() argument
5910 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); in ExtendSetCCUses()
5959 ISD::LoadExtType ExtType = in CombineExtLoad() local
5965 while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) && in CombineExtLoad()
5971 if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT)) in CombineExtLoad()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp1133 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
1134 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeOp()
1203 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { in LegalizeOp()
1214 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeOp()
1222 if (ExtType == ISD::SEXTLOAD) in LegalizeOp()
1227 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeOp()
1261 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, in LegalizeOp()
1282 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2, in LegalizeOp()
1313 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { in LegalizeOp()
1357 switch (ExtType) { in LegalizeOp()
[all …]
DLegalizeVectorTypes.cpp708 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
720 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
727 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
1879 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
1883 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
1884 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
2398 ISD::LoadExtType ExtType) { in GenWidenVectorExtLoads() argument
2421 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr, in GenWidenVectorExtLoads()
2429 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr, in GenWidenVectorExtLoads()
DLegalizeIntegerTypes.cpp414 ISD::LoadExtType ExtType = in PromoteIntRes_LOAD() local
417 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), in PromoteIntRes_LOAD()
1777 ISD::LoadExtType ExtType = N->getExtensionType(); in ExpandIntRes_LOAD() local
1788 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
1794 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
1800 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
1804 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
1821 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
1839 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
1866 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, in ExpandIntRes_LOAD()
DSelectionDAG.cpp2265 unsigned ExtType = LD->getExtensionType(); in ComputeNumSignBits() local
2266 switch (ExtType) { in ComputeNumSignBits()
4137 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
4163 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO); in getLoad()
4167 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
4172 ExtType = ISD::NON_EXTLOAD; in getLoad()
4173 } else if (ExtType == ISD::NON_EXTLOAD) { in getLoad()
4198 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile(), in getLoad()
4205 SDNode *N = new (NodeAllocator) LoadSDNode(Ops, dl, VTs, AM, ExtType, in getLoad()
4222 SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT, in getExtLoad() argument
[all …]
DDAGCombiner.cpp143 ISD::NodeType ExtType);
688 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteOperand() local
693 return DAG.getExtLoad(ExtType, dl, PVT, in PromoteOperand()
912 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteLoad() local
916 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, in PromoteLoad()
3930 ISD::NodeType ExtType) { in ExtendSetCCUses() argument
3941 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); in ExtendSetCCUses()
4606 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; in ReduceLoadWidth() local
4618 ExtType = ISD::SEXTLOAD; in ReduceLoadWidth()
4622 ExtType = ISD::ZEXTLOAD; in ReduceLoadWidth()
[all …]
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h922 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
927 SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT,
932 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
938 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT,
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAG.h655 SDValue getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
662 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
668 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h140 ISD::LoadExtType ExtType,
DR600ISelLowering.cpp1513 ISD::LoadExtType ExtType = Load->getExtensionType(); in lowerPrivateExtLoad() local
1545 if (ExtType == ISD::SEXTLOAD) { in lowerPrivateExtLoad()
1569 ISD::LoadExtType ExtType = LoadNode->getExtensionType(); in LowerLOAD() local
1572 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrInfo.td565 ISD::LoadExtType ExtType = LD->getExtensionType();
566 if (ExtType == ISD::NON_EXTLOAD)
568 if (ExtType == ISD::EXTLOAD)
575 ISD::LoadExtType ExtType = LD->getExtensionType();
576 if (ExtType == ISD::EXTLOAD)
583 ISD::LoadExtType ExtType = LD->getExtensionType();
584 if (ExtType == ISD::NON_EXTLOAD)
586 if (ExtType == ISD::EXTLOAD)
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp2567 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; in LowerFormalArguments() local
2577 ExtType = ISD::SEXTLOAD; in LowerFormalArguments()
2580 ExtType = ISD::ZEXTLOAD; in LowerFormalArguments()
2583 ExtType = ISD::EXTLOAD; in LowerFormalArguments()
2588 ExtType, DL, VA.getLocVT(), Chain, FIN, in LowerFormalArguments()
8388 unsigned ExtType = LHS.getOpcode(); in performAddSubLongCombine() local
8397 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS); in performAddSubLongCombine()
8403 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS); in performAddSubLongCombine()
9335 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) { in checkValueWidth() argument
9336 ExtType = ISD::NON_EXTLOAD; in checkValueWidth()
[all …]
DAArch64FastISel.cpp54 AArch64_AM::ShiftExtendType ExtType; member in __anon007bec610111::AArch64FastISel::Address
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend), in Address()
69 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; } in setExtendType()
70 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; } in getExtendType()
174 AArch64_AM::ShiftExtendType ExtType,
1358 AArch64_AM::ShiftExtendType ExtType, in emitAddSub_rx() argument
1394 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()

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