| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 452 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 526 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, enumerator
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| D | BasicTTIImpl.h | 785 ISDs.push_back(ISD::FCEIL); in getIntrinsicInstrCost()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 303 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in mightUseCTR()
356 Opcode = ISD::FCEIL; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 150 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
209 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
214 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
474 setOperationAction(ISD::FCEIL, VT, Expand); in PPCTargetLowering()
520 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
579 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
799 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal); in PPCTargetLowering()
804 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 184 case ISD::FCEIL: in LegalizeOp()
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| D | LegalizeFloatTypes.cpp | 68 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
851 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
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| D | LegalizeVectorTypes.cpp | 72 case ISD::FCEIL: in ScalarizeVectorResult()
448 case ISD::FCEIL: in SplitVectorResult()
1299 case ISD::FCEIL: in WidenVectorResult()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 164 case ISD::FCEIL: return "fceil"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 80 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
1020 case ISD::FCEIL: ExpandFloatRes_FCEIL(N, Lo, Hi); break; in ExpandFloatResult()
1870 case ISD::FCEIL: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 318 case ISD::FCEIL: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 78 case ISD::FCEIL: in ScalarizeVectorResult()
636 case ISD::FCEIL: in SplitVectorResult()
2154 case ISD::FCEIL: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3866 case ISD::FCEIL: in ConvertNodeToLibcall()
4222 case ISD::FCEIL: in PromoteNode()
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| D | SelectionDAG.cpp | 2964 case ISD::FCEIL: { in getNode()
3025 case ISD::FCEIL: in getNode()
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| D | SelectionDAGBuilder.cpp | 5193 case Intrinsic::ceil: Opcode = ISD::FCEIL; break; in visitIntrinsicCall()
6294 if (visitUnaryFloatCall(I, ISD::FCEIL)) in visitCall()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 87 {ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT}) in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 238 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
277 setOperationAction(ISD::FCEIL, MVT::f64, Custom); in AMDGPUTargetLowering()
411 setOperationAction(ISD::FCEIL, VT, Expand); in AMDGPUTargetLowering()
713 case ISD::FCEIL: return LowerFCEIL(Op, DAG); in LowerOperation()
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| D | SIISelLowering.cpp | 210 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in SITargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 274 setOperationAction(ISD::FCEIL, MVT::f16, Promote); in AArch64TargetLowering()
316 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand); in AArch64TargetLowering()
346 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand); in AArch64TargetLowering()
380 setOperationAction(ISD::FCEIL, Ty, Legal); in AArch64TargetLowering()
525 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand); in AArch64TargetLowering()
624 setOperationAction(ISD::FCEIL, Ty, Legal); in AArch64TargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 931 setOperationAction(ISD::FCEIL, VT, Expand); in initActions()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 380 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 450 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 510 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); in ARMTargetLowering()
527 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand); in ARMTargetLowering()
544 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand); in ARMTargetLowering()
673 setOperationAction(ISD::FCEIL, MVT::f64, Expand); in ARMTargetLowering()
989 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in ARMTargetLowering()
1003 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in ARMTargetLowering()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 364 setOperationAction(ISD::FCEIL, VT, Legal); in SystemZTargetLowering()
403 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in SystemZTargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1947 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC, in HexagonTargetLowering()
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