| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 532 FMINNUM, FMAXNUM, enumerator
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| D | BasicTTIImpl.h | 769 ISDs.push_back(ISD::FMINNUM); in getIntrinsicInstrCost()
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| D | SelectionDAG.h | 1186 case ISD::FMINNUM:
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 308 case Intrinsic::minnum: Opcode = ISD::FMINNUM; break; in mightUseCTR()
372 Opcode = ISD::FMINNUM; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 720 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal); in PPCTargetLowering()
766 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 205 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in SITargetLowering()
223 setTargetDAGCombine(ISD::FMINNUM); in SITargetLowering()
1709 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq, in LowerINTRINSIC_WO_CHAIN()
2699 case ISD::FMINNUM: in minMaxOpcToMin3Max3Opc()
2816 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) || in performMinMaxCombine()
2869 case ISD::FMINNUM: in PerformDAGCombine()
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| D | AMDGPUISelLowering.cpp | 246 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in AMDGPUTargetLowering()
408 setOperationAction(ISD::FMINNUM, VT, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 153 case ISD::FMINNUM: return "fminnum"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 77 case ISD::FMINNUM: R = SoftenFloatRes_FMINNUM(N); break; in SoftenFloatResult()
1017 case ISD::FMINNUM: ExpandFloatRes_FMINNUM(N, Lo, Hi); break; in ExpandFloatResult()
1892 case ISD::FMINNUM: in PromoteFloatResult()
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| D | LegalizeVectorOps.cpp | 303 case ISD::FMINNUM: in LegalizeOp()
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| D | SelectionDAGBuilder.cpp | 2785 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break; in visitSelect()
2787 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT)) in visitSelect()
2788 Opc = ISD::FMINNUM; in visitSelect()
2792 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()) ? in visitSelect()
2793 ISD::FMINNUM : ISD::FMINNAN; in visitSelect()
5211 : ISD::FMINNUM; in visitIntrinsicCall()
6249 if (visitBinaryFloatCall(I, ISD::FMINNUM)) in visitCall()
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| D | LegalizeVectorTypes.cpp | 110 case ISD::FMINNUM: in ScalarizeVectorResult()
675 case ISD::FMINNUM: in SplitVectorResult()
2091 case ISD::FMINNUM: in WidenVectorResult()
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| D | LegalizeDAG.cpp | 3802 case ISD::FMINNUM: in ConvertNodeToLibcall()
4184 case ISD::FMINNUM: in PromoteNode()
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| D | DAGCombiner.cpp | 1422 case ISD::FMINNUM: return visitFMINNUM(N); in visit()
5049 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM; in combineMinNumMaxNum()
5060 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM; in combineMinNumMaxNum()
9364 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0); in visitFMINNUM()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 292 setOperationAction(ISD::FMINNUM, MVT::f16, Promote); in AArch64TargetLowering()
384 setOperationAction(ISD::FMINNUM, Ty, Legal); in AArch64TargetLowering()
705 ISD::FMINNUM, ISD::FMAXNUM}) in addTypeForNEON()
8564 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
8952 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in tryMatchAcrossLaneShuffleForReduction()
9033 case ISD::FMINNUM: in tryMatchAcrossLaneShuffleForReduction()
9098 Op != ISD::UMIN && Op != ISD::FMAXNUM && Op != ISD::FMINNUM) in performAcrossLaneMinMaxReductionCombine()
9109 if (Op == ISD::FMAXNUM || Op == ISD::FMINNUM) { in performAcrossLaneMinMaxReductionCombine()
9136 (Op == ISD::FMINNUM && CC != ISD::SETOLT && CC != ISD::SETOLE && in performAcrossLaneMinMaxReductionCombine()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 868 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 433 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 994 setOperationAction(ISD::FMINNUM, MVT::f32, Legal); in ARMTargetLowering()
996 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal); in ARMTargetLowering()
998 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal); in ARMTargetLowering()
1008 setOperationAction(ISD::FMINNUM, MVT::f64, Legal); in ARMTargetLowering()
2969 ? ISD::FMINNUM : ISD::FMAXNUM; in LowerINTRINSIC_WO_CHAIN()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1949 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 631 setOperationAction(ISD::FMINNUM, MVT::f80, Expand); in X86TargetLowering()
1647 setTargetDAGCombine(ISD::FMINNUM); in X86TargetLowering()
30980 case ISD::FMINNUM: in PerformDAGCombine()
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