| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 538 FSINCOS, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 161 case ISD::FSINCOS: return "fsincos"; in getOperationName()
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| D | LegalizeDAG.cpp | 2190 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS) in useSinCos()
3154 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) || in ExpandNode()
3158 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0)); in ExpandNode()
3827 case ISD::FSINCOS: in ConvertNodeToLibcall()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 81 for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 155 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in AArch64TargetLowering()
283 setOperationAction(ISD::FSINCOS, MVT::f16, Promote); in AArch64TargetLowering()
329 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand); in AArch64TargetLowering()
361 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand); in AArch64TargetLowering()
403 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in AArch64TargetLowering()
404 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in AArch64TargetLowering()
406 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in AArch64TargetLowering()
407 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in AArch64TargetLowering()
539 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand); in AArch64TargetLowering()
2402 case ISD::FSINCOS: in LowerOperation()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1668 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in SparcTargetLowering()
1673 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in SparcTargetLowering()
1678 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in SparcTargetLowering()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrFPStack.td | 585 def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", []>, D9;
|
| D | X86GenAsmWriter.inc | 765 3180U, // FSINCOS
5873 "FPREM1\000FPTAN\000FRNDINT\000FRSTORm\000FSAVEm\000FSCALE\000FSINCOS\000"
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| D | X86GenAsmWriter1.inc | 765 2512U, // FSINCOS
6616 "FPREM1\000FPTAN\000FRNDINT\000FRSTORm\000FSAVEm\000FSCALE\000FSINCOS\000"
|
| D | X86GenInstrInfo.inc | 768 FSINCOS = 752,
4936 …{ 752, 0, 0, 0, 0, "FSINCOS", 0|(1<<MCID::UnmodeledSideEffects), 0x1f6000401ULL, NULL, NULL, 0 }, …
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| D | X86GenAsmMatcher.inc | 3522 { X86::FSINCOS, "fsincos", Convert, { }, 0},
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| D | X86GenDisassemblerTables.inc | 9043 "FSINCOS"
50424 0x2f0, /* FSINCOS*/
57443 0x2f0, /* FSINCOS*/
64608 0x2f0, /* FSINCOS*/
71773 0x2f0, /* FSINCOS*/
78938 0x2f0, /* FSINCOS*/
85962 0x2f0, /* FSINCOS*/
92981 0x2f0, /* FSINCOS*/
100000 0x2f0, /* FSINCOS*/
107019 0x2f0, /* FSINCOS*/
[all …]
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1887 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS, in HexagonTargetLowering()
1949 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, in HexagonTargetLowering()
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 766 #define FSINCOS CHOICE(fsincos, fsincos, fsincos) macro
1479 #define FSINCOS fsincos macro
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrFPStack.td | 661 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>;
|
| D | X86ISelLowering.cpp | 503 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
535 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in X86TargetLowering()
547 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in X86TargetLowering()
562 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
610 setOperationAction(ISD::FSINCOS, MVT::f80, Expand); in X86TargetLowering()
638 setOperationAction(ISD::FSINCOS, VT, Expand); in X86TargetLowering()
1606 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in X86TargetLowering()
1607 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in X86TargetLowering()
21762 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 359 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in MipsTargetLowering()
360 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in MipsTargetLowering()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 938 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in ARMTargetLowering()
939 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in ARMTargetLowering()
981 setOperationAction(ISD::FSINCOS, MVT::f64, Custom); in ARMTargetLowering()
982 setOperationAction(ISD::FSINCOS, MVT::f32, Custom); in ARMTargetLowering()
7217 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 175 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in PPCTargetLowering()
181 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in PPCTargetLowering()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 372 setOperationAction(ISD::FSINCOS, VT, Expand); in SystemZTargetLowering()
|
| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter.inc | 819 15154U, // FSINCOS
7090 0U, // FSINCOS
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| D | X86GenAsmWriter1.inc | 819 12066U, // FSINCOS
7090 0U, // FSINCOS
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| D | X86GenDisassemblerTables.inc | 10504 /* FSINCOS */
49515 0x322, /* FSINCOS */
|