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Searched refs:GetSizeInBits (Results 1 – 14 of 14) sorted by relevance

/external/vixl/src/aarch64/
Doperands-aarch64.h95 int GetSizeInBits() const { in GetSizeInBits() function
100 return GetSizeInBits(); in size()
103 return GetSizeInBits(); in SizeInBits()
241 : CPURegister(other.GetCode(), other.GetSizeInBits(), other.GetType()) { in Register()
280 VIXL_ASSERT(other.GetSizeInBits() == size_in_bits); in FixedSizeRegister()
284 : Register(other.GetCode(), other.GetSizeInBits()) { in FixedSizeRegister()
286 VIXL_ASSERT(other.GetSizeInBits() == size_in_bits); in FixedSizeRegister()
291 return Register::IsValid() && (GetSizeInBits() == size_in_bits); in IsValid()
305 : CPURegister(other.GetCode(), other.GetSizeInBits(), other.GetType()), in VRegister()
525 size_(reg1.GetSizeInBits()),
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Dassembler-aarch64.cc557 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in lslv()
558 VIXL_ASSERT(rd.GetSizeInBits() == rm.GetSizeInBits()); in lslv()
566 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in lsrv()
567 VIXL_ASSERT(rd.GetSizeInBits() == rm.GetSizeInBits()); in lsrv()
575 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in asrv()
576 VIXL_ASSERT(rd.GetSizeInBits() == rm.GetSizeInBits()); in asrv()
584 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in rorv()
585 VIXL_ASSERT(rd.GetSizeInBits() == rm.GetSizeInBits()); in rorv()
595 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in bfm()
597 Emit(SF(rd) | BFM | N | ImmR(immr, rd.GetSizeInBits()) | in bfm()
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Dmacro-assembler-aarch64.cc444 unsigned reg_size = rd.GetSizeInBits(); in MoveImmediateHelper()
512 int reg_size = dst.GetSizeInBits(); in OneInstrMoveImmediateHelper()
813 unsigned reg_size = rd.GetSizeInBits(); in LogicalMacro()
893 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() <= rd.GetSizeInBits()); in LogicalMacro()
1571 int reg_size = dst.GetSizeInBits(); in MoveImmediateForShiftedOp()
1618 VIXL_ASSERT(dst.GetSizeInBits() == src.GetSizeInBits()); in Move()
1619 VIXL_ASSERT(dst.GetSizeInBits() <= kXRegSize); in Move()
1620 int operand_size = static_cast<int>(dst.GetSizeInBits()); in Move()
1777 VIXL_ASSERT(rd.GetSizeInBits() == rn.GetSizeInBits()); in AddSubWithCarryMacro()
1792 VIXL_ASSERT(operand.GetRegister().GetSizeInBits() == rd.GetSizeInBits()); in AddSubWithCarryMacro()
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Dassembler-aarch64.h709 VIXL_ASSERT(lsb + width <= static_cast<unsigned>(rn.GetSizeInBits())); in bfi()
712 (rd.GetSizeInBits() - lsb) & (rd.GetSizeInBits() - 1), in bfi()
722 VIXL_ASSERT(lsb + width <= static_cast<unsigned>(rn.GetSizeInBits())); in bfxil()
729 VIXL_ASSERT(shift < static_cast<unsigned>(rd.GetSizeInBits())); in asr()
730 sbfm(rd, rn, shift, rd.GetSizeInBits() - 1); in asr()
739 VIXL_ASSERT(lsb + width <= static_cast<unsigned>(rn.GetSizeInBits())); in sbfiz()
742 (rd.GetSizeInBits() - lsb) & (rd.GetSizeInBits() - 1), in sbfiz()
752 VIXL_ASSERT(lsb + width <= static_cast<unsigned>(rn.GetSizeInBits())); in sbfx()
768 unsigned reg_size = rd.GetSizeInBits(); in lsl()
775 VIXL_ASSERT(shift < static_cast<unsigned>(rd.GetSizeInBits())); in lsr()
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Doperands-aarch64.cc499 VIXL_ASSERT(reg.GetSizeInBits() > static_cast<int>(kXRegSize)); in GenericOperand()
Ddebugger-aarch64.cc604 const uint64_t reg_size = target_reg.GetSizeInBits(); in PrintRegister()
626 const unsigned fpreg_size = target_fpreg.GetSizeInBits(); in PrintFPRegister()
Dmacro-assembler-aarch64.h703 Mov(rd, (rd.GetSizeInBits() == kXRegSize) ? ~imm : (~imm & kWRegMask)); in Mvn()
3340 return AcquireRegisterOfSize(reg.GetSizeInBits()); in AcquireSameSizeAs()
3344 return AcquireVRegisterOfSize(reg.GetSizeInBits()); in AcquireSameSizeAs()
Ddisasm-aarch64.cc4028 switch (reg.GetSizeInBits()) { in AppendRegisterNameToOutput()
/external/vixl/src/aarch32/
Dinstructions-aarch32.h122 int GetSizeInBits() const { return (value_ & kSizeMask) >> kSizeShift; } in GetSizeInBits() function
124 return (GetType() == kNoRegister) ? 0 : (GetSizeInBits() / 8); in GetRegSizeInBytes()
126 bool Is64Bits() const { return GetSizeInBits() == 64; } in Is64Bits()
127 bool Is128Bits() const { return GetSizeInBits() == 128; } in Is128Bits()
620 switch (reg.GetSizeInBits()) { in RegisterToList()
/external/tensorflow/tensorflow/compiler/xla/service/llvm_ir/
Dllvm_util.h134 int GetSizeInBits(llvm::Type* type);
Dllvm_util.cc204 int GetSizeInBits(llvm::Type* type) { in GetSizeInBits() function
210 bits += GetSizeInBits(element_type); in GetSizeInBits()
/external/tensorflow/tensorflow/compiler/xla/service/gpu/
Dir_emitter.cc299 int element_size = llvm_ir::GetSizeInBits(element_type); in EmitAtomicOperationUsingCAS()
Dir_emitter_unnested.cc1063 int bit_width = llvm_ir::GetSizeInBits(element_ir_type); in EmitReductionToScalar()
1505 int bit_width = llvm_ir::GetSizeInBits(element_ir_type); in EmitRowReduction()
/external/vixl/test/aarch64/
Dtest-disasm-aarch64.cc3076 v, VRegister((v.GetCode() + 1) % 32, v.GetSizeInBits(), v.GetLanes())
3078 VLIST2(v), VRegister((v.GetCode() + 2) % 32, v.GetSizeInBits(), v.GetLanes())
3080 VLIST3(v), VRegister((v.GetCode() + 3) % 32, v.GetSizeInBits(), v.GetLanes())