/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfoVector.td | 340 (LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>; 358 (A2_combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 362 (A2_combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 384 (S2_vtrunewh (vmpyh (HiReg $Rs), (HiReg $Rt)), 388 (S2_vtrunewh (vmpyh (HiReg (S2_vsxtbh $Rs)), (HiReg (S2_vsxtbh $Rt))), 401 (A2_combinew (S2_vtrunehb (M5_vmpybsu (HiReg $Rs), (HiReg $Rt))), 406 (A2_combinew (S2_vtrunehb (VMPYB_no_V5 (HiReg $Rs), (HiReg $Rt))), 453 (S2_storeri_io I32:$Rt, 0, (LoReg (S2_packhl (HiReg $Rs),
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D | HexagonCopyToCombine.cpp | 783 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local 791 .addReg(HiReg, HiRegKillFlag) in emitCombineRI() 799 .addReg(HiReg, HiRegKillFlag) in emitCombineRI() 823 .addReg(HiReg, HiRegKillFlag) in emitCombineRI() 834 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local 842 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
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D | HexagonFrameLowering.cpp | 826 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::subreg_hireg); in insertCFIInstructionsAt() local 828 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
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D | HexagonInstrInfo.td | 32 def HiReg: OutPatFrag<(ops node:$Rs), 4935 (A2_combinew (C2_mux PredRegs:$src1, (HiReg DoubleRegs:$src2), 4936 (HiReg DoubleRegs:$src3)), 5058 (HiReg $src1), 5061 (LoReg (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2))))), 5063 (HiReg $src1), 5064 (HiReg $src2)), 5065 (S2_lsr_i_p (M2_dpmpyuu_s0 (LoReg $src1), (HiReg $src2)), 32)
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D | HexagonIntrinsics.td | 766 (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>;
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | MipsExpandPseudo.cpp | 89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in ExpandBuildPairF64() local 98 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg); in ExpandBuildPairF64()
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/external/llvm/lib/Target/X86/ |
D | X86ISelDAGToDAG.cpp | 2184 unsigned SrcReg, LoReg, HiReg; in Select() local 2189 SrcReg = LoReg = X86::AL; HiReg = X86::AH; in Select() 2193 SrcReg = LoReg = X86::AX; HiReg = X86::DX; in Select() 2197 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select() 2201 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select() 2204 SrcReg = X86::EDX; LoReg = HiReg = 0; in Select() 2207 SrcReg = X86::RDX; LoReg = HiReg = 0; in Select() 2268 if (HiReg == X86::AH && Subtarget->is64Bit() && in Select() 2302 assert(HiReg && "Register for high half is not defined!"); in Select() 2303 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, in Select() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86ISelDAGToDAG.cpp | 1884 unsigned LoReg, HiReg; in Select() local 1887 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; in Select() 1888 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; in Select() 1889 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; in Select() 1890 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; in Select() 1921 if (HiReg == X86::AH && Subtarget->is64Bit() && in Select() 1951 HiReg, NVT, InFlag); in Select() 1984 unsigned LoReg, HiReg, ClrReg; in Select() local 1989 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select() 1994 LoReg = X86::AX; HiReg = X86::DX; in Select() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local 696 .addReg(HiReg); in expandBuildPairF64() 701 .addReg(HiReg); in expandBuildPairF64()
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D | MipsSEFrameLowering.cpp | 285 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local 301 std::swap(LoReg, HiReg); in expandBuildPairF64() 304 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 3965 unsigned HiReg, bool &containsReg) { in checkLowRegisterList() argument 3972 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 6102 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument 6110 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 9054 unsigned HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local 9056 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter() 9063 .addReg(HiReg).addReg(ReadAgainReg); in EmitInstrWithCustomInserter()
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