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Searched refs:I32 (Results 1 – 25 of 64) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrMemory.td61 def LOAD_I32 : I<(outs I32:$dst), (ins i32imm:$off, I32:$addr,
64 def LOAD_I64 : I<(outs I64:$dst), (ins i32imm:$off, I32:$addr,
67 def LOAD_F32 : I<(outs F32:$dst), (ins i32imm:$off, I32:$addr,
70 def LOAD_F64 : I<(outs F64:$dst), (ins i32imm:$off, I32:$addr,
77 def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr, 0)>;
78 def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr, 0)>;
79 def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr, 0)>;
80 def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr, 0)>;
83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
[all …]
DWebAssemblyInstrInteger.td59 def EQZ_I32 : I<(outs I32:$dst), (ins I32:$src),
60 [(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
62 def EQZ_I64 : I<(outs I32:$dst), (ins I64:$src),
63 [(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
69 def : Pat<(rotl I32:$lhs, (and I32:$rhs, 31)), (ROTL_I32 I32:$lhs, I32:$rhs)>;
70 def : Pat<(rotr I32:$lhs, (and I32:$rhs, 31)), (ROTR_I32 I32:$lhs, I32:$rhs)>;
76 def SELECT_I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs, I32:$cond),
77 [(set I32:$dst, (select I32:$cond, I32:$lhs, I32:$rhs))],
79 def SELECT_I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs, I32:$cond),
80 [(set I64:$dst, (select I32:$cond, I64:$lhs, I64:$rhs))],
[all …]
DWebAssemblyInstrFormats.td33 def _I32 : I<(outs I32:$dst), (ins I32:$src),
34 [(set I32:$dst, (node I32:$src))],
41 def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
42 [(set I32:$dst, (node I32:$lhs, I32:$rhs))],
65 def _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs),
66 [(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
68 def _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs),
69 [(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
73 def _F32 : I<(outs I32:$dst), (ins F32:$lhs, F32:$rhs),
74 [(set I32:$dst, (setcc F32:$lhs, F32:$rhs, cond))],
[all …]
DWebAssemblyInstrConv.td18 def I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src),
19 [(set I32:$dst, (trunc I64:$src))],
22 def I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src),
23 [(set I64:$dst, (sext I32:$src))],
25 def I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src),
26 [(set I64:$dst, (zext I32:$src))],
34 def : Pat<(i64 (anyext I32:$src)), (I64_EXTEND_U_I32 I32:$src)>;
40 def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src),
41 [(set I32:$dst, (fp_to_sint F32:$src))],
43 def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src),
[all …]
DWebAssemblyInstrFloat.td80 def SELECT_F32 : I<(outs F32:$dst), (ins F32:$lhs, F32:$rhs, I32:$cond),
81 [(set F32:$dst, (select I32:$cond, F32:$lhs, F32:$rhs))],
83 def SELECT_F64 : I<(outs F64:$dst), (ins F64:$lhs, F64:$rhs, I32:$cond),
84 [(set F64:$dst, (select I32:$cond, F64:$lhs, F64:$rhs))],
92 def : Pat<(select (i32 (setne I32:$cond, 0)), F32:$lhs, F32:$rhs),
93 (SELECT_F32 F32:$lhs, F32:$rhs, I32:$cond)>;
94 def : Pat<(select (i32 (setne I32:$cond, 0)), F64:$lhs, F64:$rhs),
95 (SELECT_F64 F64:$lhs, F64:$rhs, I32:$cond)>;
98 def : Pat<(select (i32 (seteq I32:$cond, 0)), F32:$lhs, F32:$rhs),
99 (SELECT_F32 F32:$rhs, F32:$lhs, I32:$cond)>;
[all …]
DWebAssemblyInstrControl.td19 def BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
20 [(brcond I32:$cond, bb:$dst)],
23 def BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond), [],
34 def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
35 (BR_IF bb_op:$dst, I32:$cond)>;
36 def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
37 (BR_UNLESS bb_op:$dst, I32:$cond)>;
47 def BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops),
48 [(WebAssemblybr_table I32:$index)],
82 defm : RETURN<I32>;
DWebAssemblyInstrCall.td32 def CALL_INDIRECT_#vt : I<(outs vt:$dst), (ins I32:$callee, variable_ops),
33 [(set vt:$dst, (WebAssemblycall1 I32:$callee))],
37 defm : CALL<I32, "i32.">;
45 def CALL_INDIRECT_VOID : I<(outs), (ins I32:$callee, variable_ops),
46 [(WebAssemblycall0 I32:$callee)],
DWebAssemblyInstrInfo.td103 defm : ARGUMENT<I32>;
130 defm : LOCAL<I32>;
136 def CONST_I32 : I<(outs I32:$res), (ins i32imm:$imm),
137 [(set I32:$res, imm:$imm)],
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td21 : Pat <(IntID I32:$Rs),
22 (MI I32:$Rs)>;
34 : Pat<(IntID I32:$Rs, ImmPred:$It),
35 (MI I32:$Rs, ImmPred:$It)>;
39 : Pat<(IntID ImmPred:$Is, I32:$Rt),
40 (MI ImmPred:$Is, I32:$Rt)>;
47 : Pat<(IntID I32:$Rs, I64:$Rt),
48 (MI I32:$Rs, I64:$Rt)>;
51 : Pat <(IntID I32:$Rs, I32:$Rt),
52 (MI I32:$Rs, I32:$Rt)>;
[all …]
DHexagonInstrInfoVector.td89 def: Pat<(v4i8 (HexagonVSPLATB I32:$Rs)), (S2_vsplatrb I32:$Rs)>;
93 def: Pat<(v4i16 (HexagonVSPLATH I32:$Rs)), (S2_vsplatrh I32:$Rs)>;
177 : Pat <(Op Value:$Rs, I32:$Rt),
178 (MI Value:$Rs, I32:$Rt)>;
346 def: Pat<(i64 (HexagonVSXTBH I32:$Rs)), (S2_vsxtbh I32:$Rs)>;
347 def: Pat<(i64 (HexagonVSXTBW I32:$Rs)), (S2_vsxthw I32:$Rs)>;
452 def: Pat<(truncstorev2i16 V2I32:$Rs, I32:$Rt),
453 (S2_storeri_io I32:$Rt, 0, (LoReg (S2_packhl (HiReg $Rs),
456 def: Pat<(truncstorev4i8 V4I16:$Rs, I32:$Rt),
457 (S2_storeri_io I32:$Rt, 0, (S2_vtrunehb V4I16:$Rs))>;
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_dec_DCT2_64_asm.s96 VSUB.I32 Q11, Q3, Q1
98 VADD.I32 Q10, Q3, Q1
100 VSUB.I32 Q9, Q0, Q2
102 VADD.I32 Q8, Q0, Q2
126 VADD.I32 Q13, Q8, Q15
128 VADD.I32 Q12, Q11, Q14
132 VSUB.I32 Q7, Q14, Q11
135 VSUB.I32 Q6, Q8, Q15
143 VSUB.I32 Q11, Q3, Q1
145 VADD.I32 Q10, Q3, Q1
[all …]
Dixheaacd_dct3_32.s65 VADD.I32 Q2, Q1, Q0
81 VSUB.I32 Q5, Q3, Q4
103 VADD.I32 Q2, Q1, Q0
125 VSUB.I32 Q5, Q3, Q4
158 VADD.I32 Q2, Q1, Q0
166 VSUB.I32 Q5, Q3, Q4
203 VADD.I32 Q2, Q1, Q0
217 VSUB.I32 Q5, Q3, Q4
243 VSUB.I32 D2, D2, D4
287 VADD.I32 D14, D11, D28
[all …]
Dixheaacd_post_twiddle.s131 VADD.I32 Q14, Q14, Q13
132 VSUB.I32 Q15, Q15, Q12
163 VADD.I32 Q11, Q11, Q8
166 VSUB.I32 Q10, Q9, Q10
188 VADD.I32 Q7, Q15, Q1
189 VADD.I32 Q13, Q14, Q0
202 VADD.I32 Q12, Q10, Q2
210 VADD.I32 Q8, Q11, Q8
238 VADD.I32 Q14, Q14, Q13
239 VSUB.I32 Q15, Q15, Q12
[all …]
Dixheaacd_pre_twiddle_compute.s139 VADD.I32 Q14, Q13, Q14
141 VSUB.I32 Q15, Q15, Q12
165 VADD.I32 Q10, Q10, Q9
170 VSUB.I32 Q11, Q8, Q11
208 VADD.I32 Q14, Q13, Q14
210 VSUB.I32 Q15, Q15, Q12
234 VADD.I32 Q10, Q10, Q9
239 VSUB.I32 Q11, Q8, Q11
272 VADD.I32 Q14, Q13, Q14
274 VSUB.I32 Q15, Q15, Q12
[all …]
Dixheaacd_post_twiddle_overlap.s234 VADD.I32 Q15, Q15, Q14
239 VSUB.I32 Q14, Q12, Q13
265 VADD.I32 Q14, Q14, Q0
266 VADD.I32 Q15, Q15, Q1
279 VADD.I32 Q11, Q11, Q0
281 VSUB.I32 Q12, Q13, Q12
323 VADD.I32 Q7, Q7, Q13
324 VADD.I32 Q0, Q0, Q4
486 VADD.I32 Q15, Q15, Q14
494 VSUB.I32 Q14, Q12, Q13
[all …]
Dixheaacd_calc_pre_twid.s68 VSUB.I32 D0, D12, D14
69 VSUB.I32 D2, D16, D18
70 VSUB.I32 D1, D20, D22
71 VSUB.I32 D3, D24, D26
Dixheaacd_calc_post_twid.s61 VSUB.I32 D0, D6, D8
62 VADD.I32 D1, D10, D12
63 VSUB.I32 D2, D7, D9
64 VADD.I32 D3, D11, D13
Dixheaacd_sbr_imdct_using_fft.s149 VADD.I32 q8, q0, q4
153 VSUB.I32 q9, q0, q4
160 VADD.I32 q0, q1, q5
164 VSUB.I32 q4, q1, q5
178 VADD.I32 q1, q2, q6
182 VSUB.I32 q5, q2, q6
186 VADD.I32 q2, q3, q7
190 VSUB.I32 q6, q3, q7
230 VADD.I32 q7, q14, q12
234 VSUB.I32 q3, q14, q12
[all …]
Dixheaacd_imdct_using_fft.s145 VADD.I32 q8, q0, q4
149 VSUB.I32 q9, q0, q4
156 VADD.I32 q0, q1, q5
160 VSUB.I32 q4, q1, q5
174 VADD.I32 q1, q2, q6
178 VSUB.I32 q5, q2, q6
182 VADD.I32 q2, q3, q7
186 VSUB.I32 q6, q3, q7
226 VADD.I32 q7, q14, q12
230 VSUB.I32 q3, q14, q12
[all …]
Dixheaacd_fft32x32_ld.s153 … VADD.I32 q8, q0, q4 @b_data0_r=vhaddq_s32(a_data0_r_i.val[0],a_data4_r_i.val[0])@
157 … VSUB.I32 q9, q0, q4 @b_data4_r=vhsubq_s32(a_data0_r_i.val[0],a_data4_r_i.val[0])@
164 … VADD.I32 q0, q1, q5 @b_data0_i=vhaddq_s32(a_data0_r_i.val[1],a_data4_r_i.val[1])@
168 … VSUB.I32 q4, q1, q5 @b_data4_i=vhsubq_s32(a_data0_r_i.val[1],a_data4_r_i.val[1])@
182 … VADD.I32 q1, q2, q6 @b_data2_r=vhaddq_s32(a_data2_r_i.val[0],a_data6_r_i.val[0])@
186 … VSUB.I32 q5, q2, q6 @b_data6_r=vhsubq_s32(a_data2_r_i.val[0],a_data6_r_i.val[0])@
190 … VADD.I32 q2, q3, q7 @b_data2_i=vhaddq_s32(a_data2_r_i.val[1],a_data6_r_i.val[1])@
194 … VSUB.I32 q6, q3, q7 @b_data6_i=vhsubq_s32(a_data2_r_i.val[1],a_data6_r_i.val[1])@
234 VADD.I32 q7, q14, q12 @b_data1_r=vhaddq_s32(a_data1_r,a_data5_r)@
238 VSUB.I32 q3, q14, q12 @b_data5_r=vhsubq_s32(a_data1_r,a_data5_r)@
[all …]
/external/vixl/src/aarch32/
Doperands-aarch32.cc137 } else if (dt.GetValue() == I32) { in ImmediateVbic()
162 return I32; in DecodeDt()
216 case I32: in ImmediateVmov()
303 return I32; in DecodeDt()
375 case I32: in ImmediateVmvn()
411 return I32; in DecodeDt()
459 } else if (dt.GetValue() == I32) { in ImmediateVorr()
484 return I32; in DecodeDt()
/external/v8/src/wasm/
Dwasm-opcodes.cc19 #define CASE_I32_OP(name, str) CASE_OP(I32##name, "i32." str)
47 CASE_SIGN_OP(I32, name##8, str "8") \
48 CASE_SIGN_OP(I32, name##16, str "16") \
91 CASE_CONVERT_OP(Convert, I64, I32, "i32", "extend") in OpcodeName()
92 CASE_CONVERT_OP(Convert, F32, I32, "i32", "convert") in OpcodeName()
95 CASE_CONVERT_OP(Convert, F64, I32, "i32", "convert") in OpcodeName()
159 CASE_SIGN_OP(I32, AsmjsDiv, "asmjs_div") in OpcodeName()
160 CASE_SIGN_OP(I32, AsmjsRem, "asmjs_rem") in OpcodeName()
/external/libxkbcommon/xkbcommon/test/data/symbols/
Dinet35 key <I32> { [ XF86WWW ] };
352 key <I32> { [ XF86ZoomIn ] };
374 key <I32> { [ XF86Search ] };
393 key <I32> { [ XF86Search ] };
412 key <I32> { [ XF86Search ] };
484 key <I32> { [ XF86Finance ] };
539 key <I32> { [ XF86WWW ] };
575 key <I32> { [ XF86WWW ] };
603 key <I32> { [ XF86Shop ] };
614 key <I32> { [ XF86Shop ] };
[all …]
/external/llvm/test/Transforms/ArgumentPromotion/
Dreserve-tbaa.ll28 ; CHECK: store i32 1, i32* %{{.*}}, align 4, !tbaa ![[I32:[0-9]+]]
29 ; CHECK: %g.val = load i32, i32* @g, align 4, !tbaa ![[I32]]
49 ; CHECK: ![[I32]] = !{![[I32_TYPE:[0-9]+]], ![[I32_TYPE]], i64 0}
/external/llvm/lib/Transforms/Scalar/
DLoopDataPrefetch.cpp284 Type *I32 = Type::getInt32Ty((*I)->getContext()); in runOnLoop() local
289 ConstantInt::get(I32, MemI->mayReadFromMemory() ? 0 : 1), in runOnLoop()
290 ConstantInt::get(I32, 3), ConstantInt::get(I32, 1)}); in runOnLoop()

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