| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 278 INSERT_SUBVECTOR, enumerator
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| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 749 ISD::INSERT_SUBVECTOR, 0),
751 ISD::INSERT_SUBVECTOR, 0),
753 ISD::INSERT_SUBVECTOR, 0),
755 ISD::INSERT_SUBVECTOR, 0),
757 ISD::INSERT_SUBVECTOR, 0),
759 ISD::INSERT_SUBVECTOR, 0),
761 ISD::INSERT_SUBVECTOR, 0),
763 ISD::INSERT_SUBVECTOR, 0),
765 ISD::INSERT_SUBVECTOR, 0),
767 ISD::INSERT_SUBVECTOR, 0),
[all …]
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| D | X86ISelLowering.cpp | 662 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand); in X86TargetLowering()
1111 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1301 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom); in X86TargetLowering()
1401 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); in X86TargetLowering()
1436 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom); in X86TargetLowering()
1437 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom); in X86TargetLowering()
1438 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom); in X86TargetLowering()
1439 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom); in X86TargetLowering()
1540 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom); in X86TargetLowering()
1541 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom); in X86TargetLowering()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 294 INSERT_SUBVECTOR, enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 221 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 598 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
869 Lo = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, LoVT, Lo, SubVec, Idx); in SplitVecRes_INSERT_SUBVECTOR()
3154 ISD::INSERT_SUBVECTOR, DL, FixedVT, DAG.getUNDEF(FixedVT), InOp, in WidenVecOp_EXTEND()
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| D | DAGCombiner.cpp | 1437 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N); in visit()
13217 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
13286 case ISD::INSERT_SUBVECTOR: { in simplifyShuffleOperandRecursively()
13311 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, in simplifyShuffleOperandRecursively()
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| D | LegalizeDAG.cpp | 2978 case ISD::INSERT_SUBVECTOR: in ExpandNode()
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| D | SelectionDAG.cpp | 3982 case ISD::INSERT_SUBVECTOR: { in getNode()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1955 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1982 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
2771 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG); in LowerOperation()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 471 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, in Insert128BitVector()
703 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); in X86TargetLowering()
1073 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); in X86TargetLowering()
6454 V.getOpcode() == ISD::INSERT_SUBVECTOR && in isVectorBroadcast()
10400 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); in LowerOperation()
13305 N->getOpcode() == ISD::INSERT_SUBVECTOR) { in CanFoldXORWithAllOnes()
13309 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && in CanFoldXORWithAllOnes()
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| D | X86GenDAGISel.inc | 6162 /*13513*/ OPC_SwitchOpcode /*4 cases */, 81|128,1/*209*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),//…
6516 /*14359*/ OPC_CheckOpcode, TARGET_VAL(ISD::INSERT_SUBVECTOR),
45783 /*SwitchOpcode*/ 34|128,2/*290*/, TARGET_VAL(ISD::INSERT_SUBVECTOR),// ->95887
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 565 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 3146 case ISD::INSERT_SUBVECTOR: { in getNode()
6011 case ISD::INSERT_SUBVECTOR: return "insert_subvector"; in getOperationName()
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| D | LegalizeDAG.cpp | 3223 case ISD::INSERT_SUBVECTOR: in ExpandNode()
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| D | DAGCombiner.cpp | 7040 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { in visitEXTRACT_SUBVECTOR()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 148 case ISD::INSERT_SUBVECTOR: in SITargetLowering()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 425 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR) in checkHighLaneIndex()
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| D | AArch64ISelLowering.cpp | 4902 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), in WidenVector()
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