Home
last modified time | relevance | path

Searched refs:INTEL_MASK (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_defines.h35 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) macro
44 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low))
549 #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18)
555 #define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29)
576 #define GEN8_SURFACE_MOCS_MASK INTEL_MASK(30, 24)
578 #define GEN8_SURFACE_QPITCH_MASK INTEL_MASK(14, 0)
582 #define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19)
584 #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6)
586 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2)
588 #define GEN7_SURFACE_HEIGHT_MASK INTEL_MASK(29, 16)
[all …]
Dbrw_nir.h147 #define BRW_NIR_FRAG_OUTPUT_INDEX_MASK INTEL_MASK(0, 0)
149 #define BRW_NIR_FRAG_OUTPUT_LOCATION_MASK INTEL_MASK(31, 1)
Dbrw_state_dump.c252 surf[5] & INTEL_MASK(3, 0), in dump_gen7_surface_state()
255 (surf[3] & INTEL_MASK(17, 0)) + 1, in dump_gen7_surface_state()
282 int aux_mode = surf[6] & INTEL_MASK(2, 0); in dump_gen8_surface_state()
311 surf[5] & INTEL_MASK(3, 0), in dump_gen8_surface_state()
319 (surf[3] & INTEL_MASK(17, 0)) + 1); in dump_gen8_surface_state()
Dgen7_wm_surface_state.c45 unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3); in gen7_check_surface_setup()
Dbrw_vec4_generator.cpp759 const int mask = ivb ? INTEL_MASK(22, 16) : INTEL_MASK(23, 17); in generate_tcs_get_instance_id()
1065 brw_imm_ud(ivb ? INTEL_MASK(15, 12) : INTEL_MASK(16, 13))); in generate_tcs_create_barrier_header()
Dbrw_fs_nir.cpp2324 brw_imm_ud(INTEL_MASK(16, 13))); in nir_emit_tcs_intrinsic()
Dbrw_fs.cpp5942 brw_imm_ud(INTEL_MASK(23, 17))); in run_tcs_single_patch()