| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 150 bool IsStore; in EmitInstruction() local
152 &IsStore); in EmitInstruction()
158 bool MaskAfter = IsSPFirstOperand && !IsStore; in EmitInstruction()
203 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
204 if (IsStore) in isBasePlusOffsetMemoryAccess()
205 *IsStore = false; in isBasePlusOffsetMemoryAccess()
235 if (IsStore) in isBasePlusOffsetMemoryAccess()
236 *IsStore = true; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
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| D | MipsMCNaCl.h | 21 bool *IsStore = nullptr);
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| /external/llvm/lib/Transforms/Instrumentation/ |
| D | EfficiencySanitizer.cpp | 196 bool instrumentFastpath(Instruction *I, const DataLayout &DL, bool IsStore,
650 bool IsStore; in instrumentLoadOrStore() local
654 IsStore = false; in instrumentLoadOrStore()
658 IsStore = true; in instrumentLoadOrStore()
662 IsStore = true; in instrumentLoadOrStore()
666 IsStore = true; in instrumentLoadOrStore()
680 if (IsStore) in instrumentLoadOrStore()
686 OnAccessFunc = IsStore ? EsanUnalignedStoreN : EsanUnalignedLoadN; in instrumentLoadOrStore()
692 instrumentFastpath(I, DL, IsStore, Addr, Alignment)) { in instrumentLoadOrStore()
697 OnAccessFunc = IsStore ? EsanAlignedStore[Idx] : EsanAlignedLoad[Idx]; in instrumentLoadOrStore()
[all …]
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 79 unsigned int IsStore : 1; member
366 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
372 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
675 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
691 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
699 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
764 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
969 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
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| D | PPCISelLowering.h | 578 bool IsStore, bool IsLoad) const override;
580 bool IsStore, bool IsLoad) const override;
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 37 bit IsStore = 0;
53 let TSFlags{6-6} = IsStore;
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| /external/llvm/lib/CodeGen/ |
| D | AtomicExpandPass.cpp | 51 bool IsStore, bool IsLoad);
227 bool IsStore, IsLoad; in runOnFunction() local
231 IsStore = false; in runOnFunction()
236 IsStore = true; in runOnFunction()
242 IsStore = IsLoad = true; in runOnFunction()
253 IsStore = IsLoad = true; in runOnFunction()
257 MadeChange |= bracketInstWithFences(I, FenceOrdering, IsStore, IsLoad); in runOnFunction()
324 bool IsStore, bool IsLoad) { in bracketInstWithFences() argument
327 auto LeadingFence = TLI->emitLeadingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
329 auto TrailingFence = TLI->emitTrailingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 436 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
437 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
438 unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
455 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
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| D | ARMISelLowering.h | 448 bool IsStore, bool IsLoad) const override;
450 bool IsStore, bool IsLoad) const override;
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| D | ARMLoadStoreOptimizer.cpp | 472 bool IsStore = in UpdateBaseRegUses() local
475 if (IsLoad || IsStore) { in UpdateBaseRegUses()
488 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base)) in UpdateBaseRegUses()
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| D | ARMISelLowering.cpp | 12356 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument
12366 if (!IsStore) in emitLeadingFence()
12381 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument
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| /external/clang/lib/CodeGen/ |
| D | CGAtomic.cpp | 1020 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
1039 if (IsStore) in EmitAtomicExpr()
1051 if (IsLoad || IsStore) in EmitAtomicExpr()
1076 if (!IsStore) in EmitAtomicExpr()
1080 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1097 if (!IsStore) { in EmitAtomicExpr()
1115 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 426 bool IsStore = MI->mayStore(); in buildScratchLoadStore() local
469 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildScratchLoadStore()
477 .addReg(SubReg, getDefRegState(!IsStore)) in buildScratchLoadStore()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 258 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm() local
259 unsigned AddrBase = IsStore; in SimplifyShortMoveForm()
260 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm()
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| /external/v8/src/arm64/ |
| D | instructions-arm64.cc | 43 bool Instruction::IsStore() const { in IsStore() function in v8::internal::Instruction
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| D | instructions-arm64.h | 232 bool IsStore() const;
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| D | simulator-arm64.cc | 1638 if (instr->IsStore()) { in LoadStoreHelper()
1740 if (instr->IsStore()) { in LoadStorePairHelper()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 821 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
822 if (!IsLoad && !IsStore) in canMoveMemTo()
844 bool Conflict = (L && IsStore) || S; in canMoveMemTo()
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| /external/vixl/src/aarch64/ |
| D | instructions-aarch64.cc | 97 bool Instruction::IsStore() const { in IsStore() function in vixl::aarch64::Instruction
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| D | instructions-aarch64.h | 302 bool IsStore() const;
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| D | simulator-aarch64.cc | 1392 } else if (instr->IsStore()) { in LoadStoreHelper()
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1199 AtomicOrdering Ord, bool IsStore, in emitLeadingFence() argument
1201 if (isReleaseOrStronger(Ord) && IsStore) in emitLeadingFence()
1208 AtomicOrdering Ord, bool IsStore, in emitTrailingFence() argument
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 308 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm() local
309 unsigned AddrBase = IsStore; in SimplifyShortMoveForm()
310 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9225 bool IsStore = false; in performNEONPostLDSTCombine() local
9240 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
9242 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
9244 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
9252 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
9254 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
9256 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
9270 NumVecs = 2; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
9272 NumVecs = 3; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
9274 NumVecs = 4; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
[all …]
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| /external/v8/src/compiler/ |
| D | machine-operator-reducer.cc | 930 } else if (nm.IsStore()) { in ReduceStore()
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