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Searched refs:JALR (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll32 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
43 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
53 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
63 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
73 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
83 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
93 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
104 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
119 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
135 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
[all …]
Dindirectbr.ll23 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
24 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
29 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
30 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/valgrind/none/tests/mips32/
Dbranches.stdout.exp408 J JALR JR :: 6, RSval: 0
409 J JALR JR :: 7, RSval: 1
410 J JALR JR :: 8, RSval: 2
411 J JALR JR :: 9, RSval: 3
412 J JALR JR :: 10, RSval: 4
413 J JALR JR :: 11, RSval: 5
414 J JALR JR :: 12, RSval: 6
415 J JALR JR :: 13, RSval: 7
416 J JALR JR :: 14, RSval: 8
417 J JALR JR :: 15, RSval: 9
[all …]
/external/valgrind/none/tests/mips64/
Dbranches.stdout.exp425 J JALR JR :: 6, RSval: 0
426 J JALR JR :: 7, RSval: 1
427 J JALR JR :: 8, RSval: 2
428 J JALR JR :: 9, RSval: 3
429 J JALR JR :: 10, RSval: 4
430 J JALR JR :: 11, RSval: 5
431 J JALR JR :: 12, RSval: 6
432 J JALR JR :: 13, RSval: 7
433 J JALR JR :: 14, RSval: 8
434 J JALR JR :: 15, RSval: 9
[all …]
/external/llvm/test/CodeGen/Mips/
Dlongbranch.ll79 ; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the
81 ; the opcode of the MachineInst is a JALR.
82 ; O32-R6: JALR
112 ; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the
114 ; the opcode of the MachineInst is a JALR.
Deh-return32.ll47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Deh-return64.ll48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp51 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
81 case Mips::JALR: in isCall()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsEmitGPRestore.cpp73 if (I->getOpcode() != Mips::JALR) { in runOnMachineFunction()
DMipsInstrInfo.td727 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
862 // (JALR CPURegs:$dst)>;
/external/v8/src/mips/
Dconstants-mips.h421 JALR = ((1U << 3) + 1), enumerator
926 FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) |
1265 case JALR: in IsLinkingInstruction()
1331 case JALR: in IsForbiddenAfterBranchInstr()
Dassembler-mips.cc580 ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); in IsJump()
600 GetRdField(instr) == 0 && GetFunctionField(instr) == JALR; in IsJr()
607 GetRdField(instr) != 0 && GetFunctionField(instr) == JALR; in IsJalr()
1565 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
Ddisasm-mips.cc1051 case JALR: in DecodeTypeRegisterSPECIAL()
/external/v8/src/mips64/
Dconstants-mips64.h404 JALR = ((1U << 3) + 1), enumerator
962 FunctionFieldToBitNumber(JR) | FunctionFieldToBitNumber(JALR) |
1341 case JALR: in IsLinkingInstruction()
1407 case JALR: in IsForbiddenAfterBranchInstr()
Ddisasm-mips64.cc1157 case JALR: in DecodeTypeRegisterSPECIAL()
Dassembler-mips64.cc557 ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); in IsJump()
579 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JALR; in IsJalr()
1564 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp253 case Mips::JALR: in printAlias()
/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp341 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JALR)) in expandToLongBranch()
DMipsDelaySlotFiller.cpp554 case Mips::JALR: in getEquivalentCallShort()
DMipsInstrInfo.td1886 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1887 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1905 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1921 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
2217 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
2493 // (JALR GPR32:$dst)>;
DMipsAsmPrinter.cpp109 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
DMips32r6InstrInfo.td860 def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32;
DMips64InstrInfo.td243 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_common.c142 #define JALR (HI(0) | LO(9)) macro
1708 PTR_FAIL_IF(push_inst(compiler, JALR | S(TMP_REG2) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_jump()
1971 FAIL_IF(push_inst(compiler, JALR | S(PIC_ADDR_REG) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_ijump()
1979 FAIL_IF(push_inst(compiler, JALR | S(src_r) | DA(RETURN_ADDR_REG), UNMOVABLE_INS)); in sljit_emit_ijump()
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp1707 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR); in processInstruction()
2103 JalrInst.setOpcode(Mips::JALR); in expandJalWithRegs()
2112 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR); in expandJalWithRegs()

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