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Searched refs:LOAD (Results 1 – 25 of 158) sorted by relevance

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/external/mesa3d/src/mesa/drivers/dri/i965/
Dhsw_queryobj.c43 MI_MATH_ALU2(LOAD, SRCA, R0), in mult_gpr0_by_80()
44 MI_MATH_ALU2(LOAD, SRCB, R0), in mult_gpr0_by_80()
47 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
48 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
51 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
52 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
55 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
56 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
60 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
61 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
[all …]
Dhsw_sol.c110 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2)); in tally_prims_written()
111 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
115 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
116 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
132 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
133 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0)); in tally_prims_written()
141 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
142 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0)); in tally_prims_written()
145 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
146 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
/external/llvm/test/CodeGen/ARM/
Dvector-promotion.ll6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
7 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
14 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
15 ; ASM-NEXT: vorr.i32 [[LOAD]], #0x1
16 ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32]
27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
28 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
34 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
35 ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
47 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
[all …]
D2012-08-09-neon-extload.ll21 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
22 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
36 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
53 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
54 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
68 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
69 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
82 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
83 ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
97 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
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/external/valgrind/memcheck/tests/
Dcond_ld.stderr.exp-arm3 LOAD CASE 0
8 LOAD CASE 1
13 LOAD CASE 2
18 LOAD CASE 3
23 LOAD CASE 4
40 LOAD CASE 5
57 LOAD CASE 6
74 LOAD CASE 7
91 LOAD CASE 8
102 LOAD CASE 9
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Dcond_ld.stderr.exp-64bit-non-arm3 LOAD CASE 0
8 LOAD CASE 1
13 LOAD CASE 2
18 LOAD CASE 3
23 LOAD CASE 4
40 LOAD CASE 5
57 LOAD CASE 6
74 LOAD CASE 7
91 LOAD CASE 8
102 LOAD CASE 9
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Dcond_ld.stderr.exp-32bit-non-arm3 LOAD CASE 0
8 LOAD CASE 1
13 LOAD CASE 2
18 LOAD CASE 3
23 LOAD CASE 4
40 LOAD CASE 5
57 LOAD CASE 6
74 LOAD CASE 7
91 LOAD CASE 8
102 LOAD CASE 9
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/external/mesa3d/src/gallium/drivers/swr/
Dswr_shader.cpp222 Value *vtxInput = LOAD(pVsCtx, {0, SWR_VS_CONTEXT_pVin}); in CompileVS()
229 wrap(LOAD(vtxInput, {0, 0, attrib, channel})); in CompileVS()
239 system_values.instance_id = wrap(LOAD(pVsCtx, {0, SWR_VS_CONTEXT_InstanceID})); in CompileVS()
240 system_values.vertex_id = wrap(LOAD(pVsCtx, {0, SWR_VS_CONTEXT_VertexID})); in CompileVS()
261 Value *vtxOutput = LOAD(pVsCtx, {0, SWR_VS_CONTEXT_pVout}); in CompileVS()
268 Value *val = LOAD(unwrap(outputs[attrib][channel])); in CompileVS()
318 Value *px = LOAD(GEP(hPrivateData, {0, swr_draw_context_userClipPlanes, val, 0})); in CompileVS()
319 Value *py = LOAD(GEP(hPrivateData, {0, swr_draw_context_userClipPlanes, val, 1})); in CompileVS()
320 Value *pz = LOAD(GEP(hPrivateData, {0, swr_draw_context_userClipPlanes, val, 2})); in CompileVS()
321 Value *pw = LOAD(GEP(hPrivateData, {0, swr_draw_context_userClipPlanes, val, 3})); in CompileVS()
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/external/llvm/test/CodeGen/AMDGPU/
Dtrunc-cmp-constant.ll5 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
6 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
20 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
21 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
46 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
47 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
58 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
59 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
82 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
83 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
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Dtrunc-store-i1.ll6 ; SI: s_load_dword [[LOAD:s[0-9]+]],
7 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
25 ; SI: s_load_dword [[LOAD:s[0-9]+]],
26 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dstreamout_jit.cpp52 return LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_pBuffer, buffer }); in getSOBuffer()
67 Value* enabled = TRUNC(LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_enable }), IRB()->getInt1Ty()); in oob()
70 Value* bufferSize = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_bufferSize }); in oob()
73 Value* streamOffset = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_streamOffset }); in oob()
76 Value* pitch = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_pitch }); in oob()
151 Value *vattrib = LOAD(pAttrib); in buildDecl()
194 … Value *numPrimStorageNeeded = LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_numPrimStorageNeeded }); in buildStream()
213 Value* numPrimsWritten = LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_numPrimsWritten }); in buildStream()
224 Value* pData = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_pBuffer }); in buildStream()
225 Value* streamOffset = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_streamOffset }); in buildStream()
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Dfetch_jit.cpp120 Value* streams = LOAD(mpFetchInfo,{0, SWR_FETCH_CONTEXT_pStreams}); in Create()
124 Value* indices = LOAD(mpFetchInfo,{0, SWR_FETCH_CONTEXT_pIndices}); in Create()
128 Value* pLastIndex = LOAD(mpFetchInfo,{0, SWR_FETCH_CONTEXT_pLastIndex}); in Create()
138 …vIndices = LOAD(BITCAST(indices, PointerType::get(VectorType::get(mInt8Ty, mpJitMgr->mVWidth), 0))… in Create()
149 …vIndices = LOAD(BITCAST(indices, PointerType::get(VectorType::get(mInt16Ty, mpJitMgr->mVWidth), 0)… in Create()
158 …(fetchState.bDisableIndexOOBCheck) ? vIndices = LOAD(BITCAST(indices, PointerType::get(mSimdInt32T… in Create()
168 Value* vBaseVertex = VBROADCAST(LOAD(mpFetchInfo, { 0, SWR_FETCH_CONTEXT_BaseVertex })); in Create()
169 Value* vStartVertex = VBROADCAST(LOAD(mpFetchInfo, { 0, SWR_FETCH_CONTEXT_StartVertex })); in Create()
251 Value* startVertex = LOAD(mpFetchInfo, {0, SWR_FETCH_CONTEXT_StartVertex}); in JitLoadVertices()
252 Value* startInstance = LOAD(mpFetchInfo, {0, SWR_FETCH_CONTEXT_StartInstance}); in JitLoadVertices()
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Dblend_jit.cpp449 Value* pRef = VBROADCAST(LOAD(pBlendState, { 0, SWR_BLEND_STATE_alphaTestReference })); in AlphaTest()
452 Value* pAlpha = LOAD(ppAlpha); in AlphaTest()
500 Value* pMask = LOAD(ppMask); in AlphaTest()
574 dst[i] = LOAD(pDst, { i }); in Create()
577 … constantColor[i] = VBROADCAST(LOAD(pBlendState, { 0, SWR_BLEND_STATE_constantColor, i })); in Create()
580 src[i] = LOAD(pSrc, { i }); in Create()
583 src1[i] = LOAD(pSrc1, { i }); in Create()
754 Value* oMask = LOAD(ppoMask); in Create()
762 Value* sampleMask = LOAD(pBlendState, { 0, SWR_BLEND_STATE_sampleMask}); in Create()
780 Value* pMask = LOAD(ppMask); in Create()
/external/llvm/test/tools/llvm-objdump/X86/
Dmacho-private-headers.test5 // RUN: | FileCheck %s -check-prefix=LOAD
364 LOAD: Load command 10
365 LOAD: cmd LC_LOAD_DYLIB
366 LOAD: cmdsize 48
367 LOAD: name /usr/lib/foo1.dylib (offset 24)
368 LOAD: current version 0.0.0
369 LOAD: compatibility version 0.0.0
370 LOAD: Load command 11
371 LOAD: cmd LC_LOAD_WEAK_DYLIB
372 LOAD: cmdsize 48
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/external/swiftshader/third_party/subzero/tests_lit/asan_tests/
Derrors.ll8 ; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
11 ; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
16 ; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
19 ; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
24 ; RUN: %t.pexe -o %t && %t 1 2 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
27 ; RUN: %t.pexe -o %t && %t 1 2 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
33 ; RUN: --check-prefix=GLOBAL-LOAD %s
37 ; RUN: --check-prefix=GLOBAL-LOAD %s
43 ; RUN: --check-prefix=GLOBAL-LOAD %s
47 ; RUN: --check-prefix=GLOBAL-LOAD %s
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/external/mesa3d/src/compiler/nir/
Dnir_intrinsics.h392 #define LOAD(name, srcs, num_indices, idx0, idx1, idx2, flags) \ macro
396 LOAD(uniform, 1, 2, BASE, RANGE, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
398 LOAD(ubo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
400 LOAD(input, 1, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER)
402 LOAD(per_vertex_input, 2, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_R…
409 LOAD(ssbo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
411 LOAD(output, 1, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
413 LOAD(per_vertex_output, 2, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
415 LOAD(shared, 1, 1, BASE, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
417 LOAD(push_constant, 1, 2, BASE, RANGE, xx,
/external/tensorflow/tensorflow/core/kernels/
Dsparse_matmul_op.cc267 #define LOAD(x) Eigen::internal::pload<Packet>(x); macro
404 const auto b = LOAD(inp); in MulAdd()
408 auto c1 = LOAD(*out); in MulAdd()
409 auto c2 = LOAD(*out + kNumOperands); in MulAdd()
424 auto c1 = LOAD(*out); in MulAdd3Way()
425 auto c2 = LOAD(*out + kNumOperands); in MulAdd3Way()
426 const auto b1 = LOAD(inp1); in MulAdd3Way()
430 const auto b2 = LOAD(inp2); in MulAdd3Way()
434 const auto b3 = LOAD(inp3); in MulAdd3Way()
457 auto c1 = LOAD(*out); in TwoMulAdd3Way()
[all …]
/external/libevent/
Devthread_win32.c114 #define LOAD(name) \ in evthread_win32_condvar_init() macro
116 LOAD(InitializeConditionVariable); in evthread_win32_condvar_init()
117 LOAD(SleepConditionVariableCS); in evthread_win32_condvar_init()
118 LOAD(WakeAllConditionVariable); in evthread_win32_condvar_init()
119 LOAD(WakeConditionVariable); in evthread_win32_condvar_init()
/external/v8/src/compiler/
Dmachine-operator.cc458 #define LOAD(Type) \ macro
494 MACHINE_TYPE_LIST(LOAD)
495 #undef LOAD
651 #define LOAD(Type) \ in UnalignedLoad() macro
655 MACHINE_TYPE_LIST(LOAD) in UnalignedLoad()
656 #undef LOAD in UnalignedLoad()
700 #define LOAD(Type) \ macro
704 MACHINE_TYPE_LIST(LOAD)
705 #undef LOAD
711 #define LOAD(Type) \ in ProtectedLoad() macro
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/external/llvm/test/Transforms/GVN/
Dno_speculative_loads_with_asan.ll28 ; CHECK: %[[LOAD:[^ ]+]] = load i32
29 ; CHECK: {{.*}} = ashr i32 %[[LOAD]]
55 ; CHECK-NOT: %[[LOAD:[^ ]+]] = load i32
/external/llvm/test/Transforms/InstCombine/
Dextractvalue.ll44 ; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32, i32* [[GEP]]
48 ; CHECK: call {{.*}}(i32 [[LOAD]])
50 ; CHECK: ret i32 [[LOAD]]
72 ; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i16, i16* [[GEP]]
73 ; CHECK-NEXT: ret i16 [[LOAD]]
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dextractvalue.ll44 ; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32* [[GEP]]
48 ; CHECK: call {{.*}}(i32 [[LOAD]])
50 ; CHECK: ret i32 [[LOAD]]
72 ; CHECK-NEXT: [[LOAD:%[A-Za-z0-9]+]] = load i32* [[GEP]]
73 ; CHECK-NEXT: ret i32 [[LOAD]]
/external/llvm/lib/Target/SystemZ/
DSystemZPatterns.td40 // with LOAD, OPERATOR and STORE being the read, modify and write
58 // The inserted operand is loaded using LOAD from an address of mode MODE.
98 // condition is false. Record that they are equivalent to a LOAD/select/STORE
115 // Try to use MVC instruction INSN for a load of type LOAD followed by a store
117 // LENGTH is the number of bytes loaded by LOAD.
125 // The other operand is a load of type LOAD, which accesses LENGTH bytes.
135 // LOAD/VT/LENGTH combination.
148 // Record that INSN is a LOAD AND TEST that can be used to compare
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSlotIndexes.h86 enum Slot { LOAD, USE, DEF, STORE, NUM };
196 return getSlot() == LOAD;
231 return SlotIndex(&entry(), SlotIndex::LOAD);
261 return SlotIndex(entry().getNext(), SlotIndex::LOAD);
280 if (s == SlotIndex::LOAD) {
680 SlotIndex newIndex(newEntry, SlotIndex::LOAD);
731 SlotIndex startIdx(startEntry, SlotIndex::LOAD);
732 SlotIndex endIdx(nextEntry, SlotIndex::LOAD);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DSlotIndexes.cpp79 SlotIndex blockStartIndex(back(), SlotIndex::LOAD); in runOnMachineFunction()
91 mi2iMap.insert(std::make_pair(mi, SlotIndex(back(), SlotIndex::LOAD))); in runOnMachineFunction()
100 MBBRanges[mbb->getNumber()].second = SlotIndex(back(), SlotIndex::LOAD); in runOnMachineFunction()

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