| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 104 {{al, r7, r7, LSR, 5}, false, al, "al r7 r7 LSR 5", "al_r7_r7_LSR_5"},
110 {{al, r6, r7, LSR, 11}, false, al, "al r6 r7 LSR 11", "al_r6_r7_LSR_11"},
118 {{al, r3, r11, LSR, 6}, false, al, "al r3 r11 LSR 6", "al_r3_r11_LSR_6"},
119 {{al, r3, r0, LSR, 7}, false, al, "al r3 r0 LSR 7", "al_r3_r0_LSR_7"},
120 {{al, r12, r14, LSR, 17},
126 {{al, r10, r8, LSR, 10}, false, al, "al r10 r8 LSR 10", "al_r10_r8_LSR_10"},
127 {{al, r11, r1, LSR, 12}, false, al, "al r11 r1 LSR 12", "al_r11_r1_LSR_12"},
129 {{al, r1, r3, LSR, 5}, false, al, "al r1 r3 LSR 5", "al_r1_r3_LSR_5"},
135 {{al, r0, r0, LSR, 18}, false, al, "al r0 r0 LSR 18", "al_r0_r0_LSR_18"},
136 {{al, r1, r5, LSR, 13}, false, al, "al r1 r5 LSR 13", "al_r1_r5_LSR_13"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc | 96 {{{ge, r7, r6, LSR, 20}, true, ge, "ge r7 r6 LSR 20", "ge_r7_r6_LSR_20"},
97 {{gt, r4, r6, LSR, 32}, true, gt, "gt r4 r6 LSR 32", "gt_r4_r6_LSR_32"},
98 {{hi, r6, r7, LSR, 29}, true, hi, "hi r6 r7 LSR 29", "hi_r6_r7_LSR_29"},
99 {{mi, r7, r1, LSR, 10}, true, mi, "mi r7 r1 LSR 10", "mi_r7_r1_LSR_10"},
100 {{ls, r7, r6, LSR, 14}, true, ls, "ls r7 r6 LSR 14", "ls_r7_r6_LSR_14"},
102 {{le, r3, r7, LSR, 2}, true, le, "le r3 r7 LSR 2", "le_r3_r7_LSR_2"},
103 {{mi, r2, r7, LSR, 32}, true, mi, "mi r2 r7 LSR 32", "mi_r2_r7_LSR_32"},
105 {{ne, r3, r7, LSR, 28}, true, ne, "ne r3 r7 LSR 28", "ne_r3_r7_LSR_28"},
106 {{gt, r6, r4, LSR, 13}, true, gt, "gt r6 r4 LSR 13", "gt_r6_r4_LSR_13"},
107 {{hi, r6, r5, LSR, 12}, true, hi, "hi r6 r5 LSR 12", "hi_r6_r5_LSR_12"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 104 {{eq, r10, r13, LSR, 23},
109 {{eq, r12, r13, LSR, 13},
114 {{pl, r13, r5, LSR, 12}, false, al, "pl r13 r5 LSR 12", "pl_r13_r5_LSR_12"},
119 {{al, r11, r10, LSR, 27},
124 {{le, r10, r8, LSR, 19}, false, al, "le r10 r8 LSR 19", "le_r10_r8_LSR_19"},
127 {{pl, r4, r6, LSR, 3}, false, al, "pl r4 r6 LSR 3", "pl_r4_r6_LSR_3"},
129 {{vc, r5, r8, LSR, 5}, false, al, "vc r5 r8 LSR 5", "vc_r5_r8_LSR_5"},
130 {{ne, r2, r9, LSR, 26}, false, al, "ne r2 r9 LSR 26", "ne_r2_r9_LSR_26"},
131 {{lt, r14, r0, LSR, 12}, false, al, "lt r14 r0 LSR 12", "lt_r14_r0_LSR_12"},
133 {{vc, r9, r13, LSR, 16}, false, al, "vc r9 r13 LSR 16", "vc_r9_r13_LSR_16"},
[all …]
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 131 {{ls, r13, r8, r14, LSR, 32},
141 {{ls, r14, r2, r5, LSR, 2},
151 {{le, r2, r0, r14, LSR, 3},
156 {{ne, r2, r0, r13, LSR, 15},
161 {{ge, r9, r12, r3, LSR, 8},
171 {{cs, r10, r13, r4, LSR, 5},
181 {{cs, r8, r7, r3, LSR, 9},
186 {{vc, r11, r2, r7, LSR, 30},
191 {{ge, r6, r14, r7, LSR, 19},
196 {{cc, r11, r3, r0, LSR, 20},
[all …]
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| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 126 {{al, r5, r2, r11, LSR, 5},
131 {{al, r14, r6, r10, LSR, 32},
136 {{al, r9, r6, r3, LSR, 13},
141 {{al, r14, r4, r6, LSR, 31},
146 {{al, r2, r1, r7, LSR, 14},
151 {{al, r2, r9, r12, LSR, 24},
161 {{al, r6, r10, r0, LSR, 8},
201 {{al, r1, r14, r7, LSR, 18},
211 {{al, r14, r5, r12, LSR, 1},
236 {{al, r9, r3, r14, LSR, 30},
[all …]
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| D | test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 102 const TestData kTests[] = {{{pl, r8, r11, plus, r6, LSR, 1, Offset},
107 {{le, r4, r8, plus, r5, LSR, 1, Offset},
112 {{vs, r2, r6, plus, r14, LSR, 1, Offset},
117 {{ls, r1, r7, plus, r8, LSR, 1, Offset},
122 {{ge, r14, r6, plus, r14, LSR, 1, Offset},
127 {{cs, r7, r0, plus, r7, LSR, 1, Offset},
132 {{ge, r11, r0, plus, r9, LSR, 1, Offset},
137 {{eq, r7, r10, plus, r4, LSR, 1, Offset},
142 {{al, r9, r2, plus, r3, LSR, 1, Offset},
147 {{cc, r11, r10, plus, r6, LSR, 1, Offset},
[all …]
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| D | test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 258 {{{eq, r0, r1, plus, r8, LSR, 1, Offset},
263 {{ne, r0, r1, plus, r8, LSR, 1, Offset},
268 {{cs, r0, r1, plus, r8, LSR, 1, Offset},
273 {{cc, r0, r1, plus, r8, LSR, 1, Offset},
278 {{mi, r0, r1, plus, r8, LSR, 1, Offset},
283 {{pl, r0, r1, plus, r8, LSR, 1, Offset},
288 {{vs, r0, r1, plus, r8, LSR, 1, Offset},
293 {{vc, r0, r1, plus, r8, LSR, 1, Offset},
298 {{hi, r0, r1, plus, r8, LSR, 1, Offset},
303 {{ls, r0, r1, plus, r8, LSR, 1, Offset},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-rs-a32.cc | 109 {{gt, r12, r4, LSR, r6}, false, al, "gt r12 r4 LSR r6", "gt_r12_r4_LSR_r6"},
117 {{gt, r4, r11, LSR, r4}, false, al, "gt r4 r11 LSR r4", "gt_r4_r11_LSR_r4"},
119 {{mi, r9, r14, LSR, r9}, false, al, "mi r9 r14 LSR r9", "mi_r9_r14_LSR_r9"},
120 {{ne, r5, r10, LSR, r8}, false, al, "ne r5 r10 LSR r8", "ne_r5_r10_LSR_r8"},
132 {{vc, r14, r14, LSR, r11},
139 {{vs, r13, r3, LSR, r12},
144 {{ge, r8, r11, LSR, r13},
149 {{cc, r5, r0, LSR, r10}, false, al, "cc r5 r0 LSR r10", "cc_r5_r0_LSR_r10"},
151 {{cc, r14, r1, LSR, r14},
156 {{vs, r10, r1, LSR, r1}, false, al, "vs r10 r1 LSR r1", "vs_r10_r1_LSR_r1"},
[all …]
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| D | test-assembler-negative-cond-rd-rn-operand-rm-shift-rs-a32.cc | 106 const TestData kTests[] = {{{cs, r13, r3, r15, LSR, r1},
109 {{cc, r14, r0, r15, LSR, r7},
118 {{ne, r15, r1, r12, LSR, r6},
124 {{cc, r15, r1, r15, LSR, r4},
130 {{vs, r15, r6, r11, LSR, r12},
142 {{gt, r15, r4, r13, LSR, r9},
148 {{pl, r15, r8, r9, LSR, r15},
157 {{ge, r6, r5, r15, LSR, r8},
190 {{cc, r4, r0, r15, LSR, r13},
211 {{eq, r15, r0, r11, LSR, r4},
[all …]
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc | 323 const TestLoopData kTests[] = {{{eq, r0, r0, LSR, 1},
328 {{ne, r0, r0, LSR, 1},
333 {{cs, r0, r0, LSR, 1},
338 {{cc, r0, r0, LSR, 1},
343 {{mi, r0, r0, LSR, 1},
348 {{pl, r0, r0, LSR, 1},
353 {{vs, r0, r0, LSR, 1},
358 {{vc, r0, r0, LSR, 1},
363 {{hi, r0, r0, LSR, 1},
368 {{ls, r0, r0, LSR, 1},
[all …]
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| D | test-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc | 323 const TestLoopData kTests[] = {{{eq, r0, r0, LSR, 1},
328 {{ne, r0, r0, LSR, 1},
333 {{cs, r0, r0, LSR, 1},
338 {{cc, r0, r0, LSR, 1},
343 {{mi, r0, r0, LSR, 1},
348 {{pl, r0, r0, LSR, 1},
353 {{vs, r0, r0, LSR, 1},
358 {{vc, r0, r0, LSR, 1},
363 {{hi, r0, r0, LSR, 1},
368 {{ls, r0, r0, LSR, 1},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc | 102 {{vc, r4, r4, LSR, r4}, true, vc, "vc r4 r4 LSR r4", "vc_r4_r4_LSR_r4"},
109 {{le, r5, r5, LSR, r6}, true, le, "le r5 r5 LSR r6", "le_r5_r5_LSR_r6"},
115 {{ls, r0, r0, LSR, r2}, true, ls, "ls r0 r0 LSR r2", "ls_r0_r0_LSR_r2"},
117 {{eq, r5, r5, LSR, r1}, true, eq, "eq r5 r5 LSR r1", "eq_r5_r5_LSR_r1"},
119 {{ls, r6, r6, LSR, r0}, true, ls, "ls r6 r6 LSR r0", "ls_r6_r6_LSR_r0"},
128 {{vs, r4, r4, LSR, r4}, true, vs, "vs r4 r4 LSR r4", "vs_r4_r4_LSR_r4"},
129 {{cc, r0, r0, LSR, r0}, true, cc, "cc r0 r0 LSR r0", "cc_r0_r0_LSR_r0"},
131 {{ls, r1, r1, LSR, r0}, true, ls, "ls r1 r1 LSR r0", "ls_r1_r1_LSR_r0"},
139 {{ls, r1, r1, LSR, r3}, true, ls, "ls r1 r1 LSR r3", "ls_r1_r1_LSR_r3"},
142 {{hi, r3, r3, LSR, r0}, true, hi, "hi r3 r3 LSR r0", "hi_r3_r3_LSR_r0"},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-rs-t32.cc | 105 {{al, r12, r7, LSR, r12},
121 {{al, r2, r4, LSR, r9}, false, al, "al r2 r4 LSR r9", "al_r2_r4_LSR_r9"},
138 {{al, r9, r13, LSR, r10},
148 {{al, r7, r1, LSR, r7}, false, al, "al r7 r1 LSR r7", "al_r7_r1_LSR_r7"},
149 {{al, r9, r12, LSR, r11},
169 {{al, r6, r11, LSR, r1}, false, al, "al r6 r11 LSR r1", "al_r6_r11_LSR_r1"},
174 {{al, r5, r3, LSR, r9}, false, al, "al r5 r3 LSR r9", "al_r5_r3_LSR_r9"},
179 {{al, r8, r3, LSR, r2}, false, al, "al r8 r3 LSR r2", "al_r8_r3_LSR_r2"},
187 {{al, r1, r9, LSR, r3}, false, al, "al r1 r9 LSR r3", "al_r1_r9_LSR_r3"},
188 {{al, r10, r7, LSR, r12},
[all …]
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| D | test-assembler-cond-rd-rn-operand-rm-shift-rs-a32.cc | 131 {{gt, r11, r5, r4, LSR, r11},
151 {{eq, r12, r7, r9, LSR, r7},
191 {{al, r13, r8, r7, LSR, r12},
216 {{al, r13, r14, r10, LSR, r4},
246 {{ne, r7, r5, r4, LSR, r8},
266 {{hi, r11, r12, r4, LSR, r13},
316 {{lt, r14, r0, r0, LSR, r11},
336 {{le, r4, r6, r3, LSR, r11},
351 {{pl, r7, r9, r11, LSR, r14},
391 {{lt, r5, r1, r9, LSR, r6},
[all …]
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| D | test-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc | 104 {{al, r0, r0, LSR, r0}, false, al, "al r0 r0 LSR r0", "al_r0_r0_LSR_r0"},
105 {{al, r0, r0, LSR, r1}, false, al, "al r0 r0 LSR r1", "al_r0_r0_LSR_r1"},
106 {{al, r0, r0, LSR, r2}, false, al, "al r0 r0 LSR r2", "al_r0_r0_LSR_r2"},
107 {{al, r0, r0, LSR, r3}, false, al, "al r0 r0 LSR r3", "al_r0_r0_LSR_r3"},
108 {{al, r0, r0, LSR, r4}, false, al, "al r0 r0 LSR r4", "al_r0_r0_LSR_r4"},
109 {{al, r0, r0, LSR, r5}, false, al, "al r0 r0 LSR r5", "al_r0_r0_LSR_r5"},
110 {{al, r0, r0, LSR, r6}, false, al, "al r0 r0 LSR r6", "al_r0_r0_LSR_r6"},
111 {{al, r0, r0, LSR, r7}, false, al, "al r0 r0 LSR r7", "al_r0_r0_LSR_r7"},
136 {{al, r1, r1, LSR, r0}, false, al, "al r1 r1 LSR r0", "al_r1_r1_LSR_r0"},
137 {{al, r1, r1, LSR, r1}, false, al, "al r1 r1 LSR r1", "al_r1_r1_LSR_r1"},
[all …]
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 837 const TestLoopData kTests[] = {{{eq, r0, r0, r0, LSR, 1},
842 {{ne, r0, r0, r0, LSR, 1},
847 {{cs, r0, r0, r0, LSR, 1},
852 {{cc, r0, r0, r0, LSR, 1},
857 {{mi, r0, r0, r0, LSR, 1},
862 {{pl, r0, r0, r0, LSR, 1},
867 {{vs, r0, r0, r0, LSR, 1},
872 {{vc, r0, r0, r0, LSR, 1},
877 {{hi, r0, r0, r0, LSR, 1},
882 {{ls, r0, r0, r0, LSR, 1},
[all …]
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| D | test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 837 const TestLoopData kTests[] = {{{eq, r0, r0, r0, LSR, 1},
842 {{ne, r0, r0, r0, LSR, 1},
847 {{cs, r0, r0, r0, LSR, 1},
852 {{cc, r0, r0, r0, LSR, 1},
857 {{mi, r0, r0, r0, LSR, 1},
862 {{pl, r0, r0, r0, LSR, 1},
867 {{vs, r0, r0, r0, LSR, 1},
872 {{vc, r0, r0, r0, LSR, 1},
877 {{hi, r0, r0, r0, LSR, 1},
882 {{ls, r0, r0, r0, LSR, 1},
[all …]
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| /external/icu/android_icu4j/src/main/java/android/icu/impl/locale/ |
| D | XLikelySubtags.java | 106 public static class LSR {
114 public static LSR from(String language, String script, String region) {
115 return new LSR(language, script, region);
144 static LSR from(String languageIdentifier) {
152 return p2.length() < 4 ? new LSR(lang, "", p2) : new LSR(lang, p2, p3);
162 public static LSR from(ULocale locale) {
163 return new LSR(locale.getLanguage(), locale.getScript(), locale.getCountry());
166 public static LSR fromMaximalized(ULocale locale) {
170 public static LSR fromMaximalized(String language, String script, String region) {
178 public LSR(String language, String script, String region) {
[all …]
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| D | XLocaleMatcher.java | 17 import android.icu.impl.locale.XLikelySubtags.LSR;
29 private static final LSR UND = new LSR("und","","");
41 …private final Map<LSR, Set<ULocale>> supportedLanguages; // the locales in the collection are orde…
157 Set<LSR> paradigms = extractLsrSet(localeDistance.getParadigms()); in XLocaleMatcher()
158 … final Multimap<LSR, ULocale> temp2 = extractLsrMap(builder.supportedLanguagesList, paradigms); in XLocaleMatcher()
170 private Set<LSR> extractLsrSet(Set<ULocale> languagePriorityList) {
171 Set<LSR> result = new LinkedHashSet<LSR>();
173 final LSR max = item.equals(UND_LOCALE) ? UND : LSR.fromMaximalized(item);
179 …private Multimap<LSR,ULocale> extractLsrMap(Set<ULocale> languagePriorityList, Set<LSR> priorities…
180 Multimap<LSR, ULocale> builder = LinkedHashMultimap.create();
[all …]
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| /external/icu/icu4j/main/classes/core/src/com/ibm/icu/impl/locale/ |
| D | XLikelySubtags.java | 102 public static class LSR {
110 public static LSR from(String language, String script, String region) {
111 return new LSR(language, script, region);
140 static LSR from(String languageIdentifier) {
148 return p2.length() < 4 ? new LSR(lang, "", p2) : new LSR(lang, p2, p3);
158 public static LSR from(ULocale locale) {
159 return new LSR(locale.getLanguage(), locale.getScript(), locale.getCountry());
162 public static LSR fromMaximalized(ULocale locale) {
166 public static LSR fromMaximalized(String language, String script, String region) {
174 public LSR(String language, String script, String region) {
[all …]
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| D | XLocaleMatcher.java | 16 import com.ibm.icu.impl.locale.XLikelySubtags.LSR;
27 private static final LSR UND = new LSR("und","","");
39 …private final Map<LSR, Set<ULocale>> supportedLanguages; // the locales in the collection are orde…
155 Set<LSR> paradigms = extractLsrSet(localeDistance.getParadigms()); in XLocaleMatcher()
156 … final Multimap<LSR, ULocale> temp2 = extractLsrMap(builder.supportedLanguagesList, paradigms); in XLocaleMatcher()
168 private Set<LSR> extractLsrSet(Set<ULocale> languagePriorityList) {
169 Set<LSR> result = new LinkedHashSet<LSR>();
171 final LSR max = item.equals(UND_LOCALE) ? UND : LSR.fromMaximalized(item);
177 …private Multimap<LSR,ULocale> extractLsrMap(Set<ULocale> languagePriorityList, Set<LSR> priorities…
178 Multimap<LSR, ULocale> builder = LinkedHashMultimap.create();
[all …]
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| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_complex_fft_p2.s | 27 AND r7, r4, r0, LSR #2
30 AND r7, r5, r4, LSR #4
34 MOV r7, r7, LSR #8
37 MOV r10, r4, LSR r12
187 LSR r3, r3, #31
190 LSR r3, r3, #31
193 LSR r3, r3, #31
196 LSR r3, r3, #31
205 LSR r3, r3, #31
208 LSR r3, r3, #31
[all …]
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| D | ixheaacd_complex_ifft_p2.s | 27 AND r7, r4, r0, LSR #2
30 AND r7, r5, r4, LSR #4
34 MOV r7, r7, LSR #8
37 MOV r10, r4, LSR r12
187 LSR r3, r3, #31
190 LSR r3, r3, #31
193 LSR r3, r3, #31
196 LSR r3, r3, #31
205 LSR r3, r3, #31
208 LSR r3, r3, #31
[all …]
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| D | ixheaacd_mps_complex_fft_64_asm.s | 27 LDRB r10, [r12, r0, LSR #2]
175 LSR r3, r3, #31
178 LSR r3, r3, #31
181 LSR r3, r3, #31
184 LSR r3, r3, #31
193 LSR r3, r3, #31
196 LSR r3, r3, #31
199 LSR r3, r3, #31
202 LSR r3, r3, #31
211 LSR r3, r3, #31
[all …]
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| /external/llvm/test/Transforms/LoopStrengthReduce/ARM/ |
| D | 2012-06-15-lsr-noaddrmode.ll | 3 ; LSR should only check for valid address modes when the IV user is a
11 ; LSR before the fix:
13 ; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
15 ; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32
17 ; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
19 ; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32*
21 ; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
24 ; LSR after the fix:
26 ; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32
28 ; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32
[all …]
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