| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 54 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || in isLoadFromStackSlot()
205 Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1; in loadRegFromStackSlot()
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| D | MipsInstrFPU.td | 201 def LWC1 : FPLoad<0x31, "lwc1", load, FGR32, mem>;
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 217 case Mips::LWC1: in isBasePlusOffsetMemoryAccess()
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| /external/valgrind/none/tests/mips32/ |
| D | vfp.stdout.exp-mips32-BE | 29 LWC1
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| D | vfp.stdout.exp-mips32-LE | 29 LWC1
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| D | vfp.stdout.exp-mips32r2-BE | 29 LWC1
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| D | vfp.stdout.exp-mips32r2-LE | 29 LWC1
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| D | vfp.stdout.exp-mips32r2-fpu_64-LE | 29 LWC1
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| D | vfp.stdout.exp-mips32r2-fpu_64-BE | 29 LWC1
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| /external/v8/src/mips/ |
| D | constants-mips.h | 385 LWC1 = ((6U << 3) + 1) << kOpcodeShift, enumerator
918 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
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| D | assembler-mips.cc | 2222 GenInstrImmediate(LWC1, src.rm(), fd, src.offset_); in lwc1()
2225 GenInstrImmediate(LWC1, at, fd, off16); in lwc1()
2235 GenInstrImmediate(LWC1, src.rm(), fd, in ldc1()
2239 GenInstrImmediate(LWC1, src.rm(), nextfpreg, in ldc1()
2243 GenInstrImmediate(LWC1, at, fd, off16 + Register::kMantissaOffset); in ldc1()
2246 GenInstrImmediate(LWC1, at, nextfpreg, off16 + Register::kExponentOffset); in ldc1()
2253 GenInstrImmediate(LWC1, src.rm(), fd, in ldc1()
2260 GenInstrImmediate(LWC1, at, fd, off16 + Register::kMantissaOffset); in ldc1()
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| D | disasm-mips.cc | 1645 case LWC1: in DecodeTypeImmediate()
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| D | simulator-mips.cc | 4516 case LWC1: in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 364 LWC1 = ((6U << 3) + 1) << kOpcodeShift, enumerator
953 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
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| D | disasm-mips64.cc | 1862 case LWC1: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 2602 GenInstrImmediate(LWC1, src.rm(), fd, src.offset_); in lwc1()
2605 GenInstrImmediate(LWC1, at, fd, off16); in lwc1()
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| D | simulator-mips64.cc | 4782 case LWC1: in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
278 Opc = Mips::LWC1; in loadRegFromStack()
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| D | MipsInstrFPU.td | 404 def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, mem_simm16, II_LWC1, load>,
647 def : LoadRegImmPat<LWC1, f32, load>;
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| D | MipsFastISel.cpp | 743 Opc = Mips::LWC1; in emitLoad()
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| /external/llvm/test/MC/Mips/ |
| D | target-soft-float.s | 274 # FIXME: LWC1 is correctly rejected but the wrong error message is emitted.
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 970 12599389U, // LWC1
2684 0U, // LWC1
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| D | MipsGenDisassemblerTables.inc | 3606 /* 13233 */ MCD_OPC_Decode, 185, 7, 196, 1, // Opcode: LWC1
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| /external/valgrind/none/tests/mips64/ |
| D | fpu_load_store.stdout.exp-BE | 771 --- LWC1 ---
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| D | fpu_load_store.stdout.exp-LE | 771 --- LWC1 ---
|