Searched refs:LWL (Results 1 – 19 of 19) sorted by relevance
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 221 case Mips::LWL: in isBasePlusOffsetMemoryAccess()
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| /external/v8/src/mips/ |
| D | constants-mips.h | 374 LWL = ((4U << 3) + 2) << kOpcodeShift, enumerator
914 OpcodeToBitNumber(LB) | OpcodeToBitNumber(LH) | OpcodeToBitNumber(LWL) |
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| D | disasm-mips.cc | 1612 case LWL: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 1891 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
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| D | simulator-mips.cc | 4454 case LWL: { in DecodeTypeImmediate()
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| /external/v8/src/mips64/ |
| D | constants-mips64.h | 349 LWL = ((4U << 3) + 2) << kOpcodeShift, enumerator
947 OpcodeToBitNumber(LWL) | OpcodeToBitNumber(LW) | OpcodeToBitNumber(LWU) |
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| D | disasm-mips64.cc | 1814 case LWL: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 2063 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
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| D | simulator-mips64.cc | 4669 case LWL: { in DecodeTypeImmediate()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator
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| D | MipsISelLowering.cpp | 147 case MipsISD::LWL: return "MipsISD::LWL"; in getTargetNodeName()
2294 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, in lowerLOAD() local
2296 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD()
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| D | MipsInstrInfo.td | 132 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
1767 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 975 12605051U, // LWL
2689 0U, // LWL
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| D | MipsGenDisassemblerTables.inc | 3570 /* 13077 */ MCD_OPC_Decode, 190, 7, 194, 1, // Opcode: LWL
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| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-BE | 257 LWL
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| D | MIPS32int.stdout.exp-mips32-LE | 257 LWL
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| D | MIPS32int.stdout.exp-mips32r2-LE | 643 LWL
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| D | MIPS32int.stdout.exp-mips32r2-BE | 643 LWL
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3306 TOut.emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc, in expandUlw()
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