/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfoVector.td | 256 (LoReg (A2_vaddub (Zext64 $Rs), (Zext64 $Rt)))>; 261 (LoReg (A2_vsubub (Zext64 $Rs), (Zext64 $Rt)))>; 267 (LoReg (C2_vmux I1:$Pu, (Zext64 $Rs), (Zext64 $Rt)))>; 269 (LoReg (C2_vmux I1:$Pu, (Zext64 $Rs), (Zext64 $Rt)))>; 340 (LoReg (S2_packhl (HiReg $Rs), (LoReg $Rs)))>; 358 (A2_combinew (A2_sxtb (HiReg $Rs)), (A2_sxtb (LoReg $Rs)))>; 362 (A2_combinew (A2_sxth (HiReg $Rs)), (A2_sxth (LoReg $Rs)))>; 379 (LoReg (S2_vtrunewh (v2i32 (A2_combineii 0, 0)), 385 (vmpyh (LoReg $Rs), (LoReg $Rt)))>; 389 (vmpyh (LoReg (S2_vsxtbh $Rs)), (LoReg (S2_vsxtbh $Rt))))>; [all …]
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D | HexagonCopyToCombine.cpp | 734 unsigned LoReg = LoOperand.getReg(); in emitCombineIR() local 745 .addReg(LoReg, LoRegKillFlag); in emitCombineIR() 753 .addReg(LoReg, LoRegKillFlag); in emitCombineIR() 760 .addReg(LoReg, LoRegKillFlag); in emitCombineIR() 768 .addReg(LoReg, LoRegKillFlag); in emitCombineIR() 775 .addReg(LoReg, LoRegKillFlag); in emitCombineIR() 833 unsigned LoReg = LoOperand.getReg(); in emitCombineRR() local 843 .addReg(LoReg, LoRegKillFlag); in emitCombineRR()
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D | HexagonInstrInfo.td | 30 def LoReg: OutPatFrag<(ops node:$Rs), 3197 (M2_dpmpyss_s0 (LoReg DoubleRegs:$src1), (LoReg DoubleRegs:$src2))>; 3621 defm: Storexm_pat<truncstorei8, I64, s32_0ImmPred, LoReg, S2_storerb_io>; 3622 defm: Storexm_pat<truncstorei16, I64, s31_1ImmPred, LoReg, S2_storerh_io>; 3623 defm: Storexm_pat<truncstorei32, I64, s30_2ImmPred, LoReg, S2_storeri_io>; 3626 def: Storexm_simple_pat<truncstorei8, I64, LoReg, S2_storerb_io>; 3627 def: Storexm_simple_pat<truncstorei16, I64, LoReg, S2_storerh_io>; 3628 def: Storexm_simple_pat<truncstorei32, I64, LoReg, S2_storeri_io>; 4264 (S2_tstbit_i (LoReg DoubleRegs:$Rs), 0)>; 4899 (A2_sxtw (LoReg DoubleRegs:$src1))>; [all …]
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D | HexagonFrameLowering.cpp | 827 unsigned LoReg = HRI.getSubReg(Reg, Hexagon::subreg_loreg); in insertCFIInstructionsAt() local 829 unsigned LoDwarfReg = HRI.getDwarfRegNum(LoReg, true); in insertCFIInstructionsAt()
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D | HexagonInstrInfoV5.td | 794 (LoReg (F2_conv_df2d_chop F64:$src1))>,
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D | HexagonIntrinsics.td | 766 (A2_combinew (HiReg I64:$src), (LoReg I64:$src))>;
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D | HexagonInstrInfoV4.td | 3872 def: Stoream_pat<truncstorei32, I64, addrga, LoReg, S2_storeriabs>;
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | MipsExpandPseudo.cpp | 89 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in ExpandBuildPairF64() local 97 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg); in ExpandBuildPairF64()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86ISelDAGToDAG.cpp | 1838 unsigned LoReg; in Select() local 1841 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; in Select() 1842 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; in Select() 1843 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; in Select() 1844 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; in Select() 1847 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select() 1884 unsigned LoReg, HiReg; in Select() local 1887 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; in Select() 1888 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; in Select() 1889 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; in Select() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86ISelDAGToDAG.cpp | 2137 unsigned LoReg; in Select() local 2140 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; in Select() 2141 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; in Select() 2142 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; in Select() 2143 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; in Select() 2146 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, in Select() 2184 unsigned SrcReg, LoReg, HiReg; in Select() local 2189 SrcReg = LoReg = X86::AL; HiReg = X86::AH; in Select() 2193 SrcReg = LoReg = X86::AX; HiReg = X86::DX; in Select() 2197 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select() [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsSEFrameLowering.cpp | 284 unsigned LoReg = I->getOperand(1).getReg(); in expandBuildPairF64() local 301 std::swap(LoReg, HiReg); in expandBuildPairF64() 302 TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, in expandBuildPairF64()
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D | MipsSEInstrInfo.cpp | 651 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local 680 .addReg(LoReg); in expandBuildPairF64()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 9053 unsigned LoReg = MI.getOperand(0).getReg(); in EmitInstrWithCustomInserter() local 9057 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268); in EmitInstrWithCustomInserter()
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