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Searched refs:M0 (Results 1 – 25 of 181) sorted by relevance

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/external/mesa3d/src/mesa/sparc/
Dsparc_matrix.h35 #define M0 %f16 macro
53 ldd [BASE + ( 0 * 0x4)], M0; \
59 ldd [BASE + ( 0 * 0x4)], M0; \
63 ld [BASE + ( 0 * 0x4)], M0; \
67 ldd [BASE + ( 0 * 0x4)], M0; \
73 ld [BASE + ( 0 * 0x4)], M0; \
78 ld [BASE + ( 0 * 0x4)], M0; \
82 ldd [BASE + ( 0 * 0x4)], M0; \
90 ld [BASE + ( 0 * 0x4)], M0; \
95 ldd [BASE + ( 0 * 0x4)], M0; \
[all …]
Dxform.S82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
86 fmuls %f8, M0, %f9 ! FGM Group f1 available
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
197 fmuls %f0, M0, %f1 ! FGM Group
199 fmuls %f8, M0, %f9 ! FGM Group
218 fmuls %f0, M0, %f1
251 fmuls %f0, M0, %f1 ! FGM Group
252 fmuls %f4, M0, %f5 ! FGM Group
268 fmuls %f0, M0, %f1
299 fmuls %f0, M0, %f1 ! FGM Group
[all …]
Dnorm.S60 fmuls %f0, M0, %f3 ! FGM Group
104 fmuls M0, %f15, M0
125 fmuls %f0, M0, %f3 ! FGM Group
199 fmuls %f0, M0, %f3 ! FGM Group
231 fmuls M0, %f15, M0
246 fmuls %f0, M0, %f3 ! FGM Group
291 fmuls M0, %f15, M0
305 fmuls %f0, M0, %f3 ! FGM Group
342 fmuls M0, %f15, M0
358 fmuls %f0, M0, %f3 ! FGM Group
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Support/
DCommandLine.h1174 explicit opt(const M0t &M0) : Option(Optional | NotHidden) {
1175 apply(M0, this);
1181 opt(const M0t &M0, const M1t &M1) : Option(Optional | NotHidden) {
1182 apply(M0, this); apply(M1, this);
1188 opt(const M0t &M0, const M1t &M1,
1190 apply(M0, this); apply(M1, this); apply(M2, this);
1195 opt(const M0t &M0, const M1t &M1, const M2t &M2,
1197 apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
1202 opt(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3,
1204 apply(M0, this); apply(M1, this); apply(M2, this); apply(M3, this);
[all …]
/external/clang/test/Preprocessor/
Dbigoutput.c8 #define M0 extern int x; macro
9 #define M2 M0 M0 M0 M0
/external/llvm/unittests/Support/
DCommandLineTest.cpp54 explicit StackOption(const M0t &M0) : Base(M0) {} in StackOption() argument
58 StackOption(const M0t &M0, const M1t &M1) : Base(M0, M1) {} in StackOption() argument
62 StackOption(const M0t &M0, const M1t &M1, const M2t &M2) : Base(M0, M1, M2) {} in StackOption() argument
66 StackOption(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3) in StackOption() argument
67 : Base(M0, M1, M2, M3) {} in StackOption()
/external/boringssl/src/crypto/fipsmodule/bn/asm/
Darmv4-mont.pl299 my ($Bi,$Ni,$M0)=map("d$_",(28..31));
330 vld1.32 {${M0}[0]}, [$n0,:32]
342 vmul.u32 $Ni,$Ni,$M0
392 vmul.u32 $Ni,$Ni,$M0
463 vld1.32 {${M0}[0]},[$n0,:32]
483 vmul.u32 $Ni,$Ni,$M0
520 vmul.u32 $Ni,$Ni,$M0
/external/boringssl/src/crypto/fipsmodule/ec/asm/
Dp256-x86_64-asm.pl948 my ($M0,$T0a,$T0b,$T0c,$T0d,$T0e,$T0f,$TMP0)=map("%xmm$_",(8..15));
991 movdqa $ONE, $M0
997 movdqa $M0, $TMP0
998 paddd $ONE, $M0
1079 movdqa .LOne(%rip), $M0
1087 movdqa $M0, $ONE
1092 movdqa $M0, $TMP0
1093 paddd $ONE, $M0
1141 my ($M0,$T0a,$T0b,$T0c,$TMP0)=map("%ymm$_",(5..9));
1175 vmovdqa .LOne(%rip), $M0
[all …]
/external/boringssl/src/crypto/poly1305/
Dpoly1305_vec.c236 xmmi M0, M1, M2, M3, M4; in poly1305_blocks() local
299 M0 = _mm_and_si128(MMASK, T5); in poly1305_blocks()
307 T5 = _mm_mul_epu32(M0, p->R20.v); in poly1305_blocks()
308 T6 = _mm_mul_epu32(M0, p->R21.v); in poly1305_blocks()
327 T5 = _mm_mul_epu32(M0, p->R22.v); in poly1305_blocks()
328 T6 = _mm_mul_epu32(M0, p->R23.v); in poly1305_blocks()
347 T5 = _mm_mul_epu32(M0, p->R24.v); in poly1305_blocks()
363 M0 = _mm_and_si128(MMASK, T5); in poly1305_blocks()
370 T0 = _mm_add_epi64(T0, M0); in poly1305_blocks()
425 xmmi M0, M1, M2, M3, M4; in poly1305_combine() local
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.td124 // C6 and C7 can also be M0 and M1, but register names must be unique, even
126 def M0 : Mx<0, "m0">, DwarfRegNum<[72]>;
148 def C6 : Rc<6, "c6", [], [M0]>, DwarfRegNum<[73]>;
255 def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>;
261 M0, M1, C6, C7, CS0, CS1, UPCL, UPCH,
272 M0, M1,
/external/llvm/test/Assembler/
Dmetadata.ll9 ; CHECK: ret void, !foo [[M0:![0-9]+]], !bar [[M1:![0-9]+]]
38 ; CHECK: [[M0]] = !DILocation
/external/llvm/unittests/Linker/
DLinkModulesTest.cpp265 MDNode *M0 = F->getMetadata("attach"); in TEST_F() local
273 EXPECT_TRUE(M0->isDistinct()); in TEST_F()
294 EXPECT_EQ(M0, F->getMetadata("attach")); in TEST_F()
301 EXPECT_TRUE(M0->isDistinct()); in TEST_F()
/external/swiftshader/third_party/LLVM/unittests/Analysis/
DScalarEvolutionTest.cpp64 const SCEVMulExpr *M0 = cast<SCEVMulExpr>(P0); in TEST_F() local
68 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(), in TEST_F()
76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
/external/llvm/unittests/Analysis/
DScalarEvolutionTest.cpp73 const SCEVMulExpr *M0 = cast<SCEVMulExpr>(P0); in TEST_F() local
77 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(), in TEST_F()
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
94 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0); in TEST_F()
/external/llvm/test/CodeGen/ARM/
Dbuild-attributes.ll71 …thumbv6m-linux-gnueabi -mcpu=cortex-m0 -mattr=+strict-align | FileCheck %s --check-prefix=CORTEX-M0
72 …infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST
841 ; CORTEX-M0: .cpu cortex-m0
842 ; CORTEX-M0: .eabi_attribute 6, 12
843 ; CORTEX-M0-NOT: .eabi_attribute 7
844 ; CORTEX-M0: .eabi_attribute 8, 0
845 ; CORTEX-M0: .eabi_attribute 9, 1
846 ; CORTEX-M0-NOT: .eabi_attribute 19
848 ; CORTEX-M0: .eabi_attribute 20, 1
849 ; CORTEX-M0: .eabi_attribute 21, 1
[all …]
/external/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp456 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in emitLoadM0FromVGPRLoop()
461 .addReg(AMDGPU::M0) in emitLoadM0FromVGPRLoop()
469 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) in emitLoadM0FromVGPRLoop()
470 .addReg(AMDGPU::M0) in emitLoadM0FromVGPRLoop()
535 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0) in loadM0()
539 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in loadM0()
DSIRegisterInfo.td45 def M0 : SIReg <"m0", 124>;
256 // Subset of SReg_32 without M0 for SMRD instructions and alike.
266 (add SReg_32_XM0, M0)> {
DSILoadStoreOptimizer.cpp261 LiveRange &M0Range = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::M0, TRI)); in mergeRead2Pair()
329 LiveRange &M0Range = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::M0, TRI)); in mergeWrite2Pair()
DSIISelLowering.cpp1032 .Case("m0", AMDGPU::M0) in getRegisterByName()
1054 case AMDGPU::M0: in getRegisterByName()
1137 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0) in EmitInstrWithCustomInserter()
1618 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue, in copyToM0() local
1620 return SDValue(M0, 0); in copyToM0()
1817 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN() local
1818 SDValue Glue = M0.getValue(1); in LowerINTRINSIC_WO_CHAIN()
1833 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3)); in LowerINTRINSIC_WO_CHAIN() local
1834 SDValue Glue = M0.getValue(1); in LowerINTRINSIC_WO_CHAIN()
1843 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4)); in LowerINTRINSIC_WO_CHAIN() local
[all …]
/external/llvm/test/CodeGen/Thumb/
D2012-04-26-M0ISelBug.ll2 ; Cortex-M0 doesn't have 32-bit Thumb2 instructions (except for dmb, mrs, etc.)
/external/llvm/test/CodeGen/X86/
Dshuffle-combine-crash.ll5 ; (shuffle (shuffle A, Undef, M0), Undef, M1) -> (shuffle A, Undef, M2)
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.td134 defm M0 : Rss<2, 4, "m0">;
135 def M0 : Rii<2, 4, "m0", [M0H, M0L]>, DwarfRegNum<[20]>;
238 def M : RegisterClass<"BF", [i32], 32, (add M0, M1, M2, M3)>;
/external/perf_data_converter/src/quipper/testdata/
Dperf.data.piped.intel_pt-4.14.pr.out.pb_text5104 …M0\370\326KYI\324\030-0\356\336\212\202\010-0\370\324\030-0\356\336\212\200\030-0\370\324\030-0\35…
6057 …M0[\325KY=\352\252\240\314\324\324\324`\000-\234\213Y>\206\206\332\252\252\224\324\336\nY?dM\220\3…
/external/python/cpython3/PC/icons/
Dsetup.svg1 ….949-2h12.998l.949 2H1.959zM6 22v-1h3v-2h1v2h3v1H6z"/><path class="st1" d="M0 7v12h19V7H0zm18 11H1…
/external/ltp/testcases/kernel/syscalls/ptrace/
Dptrace04.c37 R(M0) R(M1) R(M2) R(M3)

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