Searched refs:MASK1 (Results 1 – 5 of 5) sorted by relevance
| /external/syslinux/com32/lua/src/ |
| D | lopcodes.h | 80 #define MASK1(n,p) ((~((~(Instruction)0)<<(n)))<<(p)) macro
83 #define MASK0(n,p) (~MASK1(n,p))
89 #define GET_OPCODE(i) (cast(OpCode, ((i)>>POS_OP) & MASK1(SIZE_OP,0)))
91 ((cast(Instruction, o)<<POS_OP)&MASK1(SIZE_OP,POS_OP))))
93 #define getarg(i,pos,size) (cast(int, ((i)>>pos) & MASK1(size,0)))
95 ((cast(Instruction, v)<<pos)&MASK1(size,pos))))
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | unal-altivec.ll | 36 ; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
44 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
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| /external/mesa3d/src/mesa/program/ |
| D | program_lexer.l | 378 return MASK1;
435 return_token_or_DOT(require_ARB_fp, MASK1);
446 return MASK1;
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| D | program_parse.y | 193 %token <swiz_mask> MASK4 MASK3 MASK2 MASK1 SWIZZLE
934 addrComponent: MASK1
945 addrWriteMask: MASK1
957 scalarSuffix: MASK1;
959 swizzleSuffix: MASK1
965 optionalMask: MASK4 | MASK3 | MASK2 | MASK1
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | uniform-cfg.ll | 310 ; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
340 ; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
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