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Searched refs:MCSchedClassDesc (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/CodeGen/
DTargetSchedule.cpp77 const MCSchedClassDesc *SC) const { in getNumMicroOps()
101 const MCSchedClassDesc *TargetSchedModel::
106 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
187 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
199 const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI); in computeOperandLatency()
226 TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const { in computeInstrLatency()
242 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx); in computeInstrLatency()
260 const MCSchedClassDesc *SCDesc = resolveSchedClass(MI); in computeInstrLatency()
290 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOutputLatency()
DMachineCombiner.cpp81 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC);
293 SmallVectorImpl<const MCSchedClassDesc *> &InstrsSC) { in instr2instrSC()
297 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx); in instr2instrSC()
318 SmallVector<const MCSchedClassDesc *, 16> InsInstrsSC; in preservesResourceLen()
319 SmallVector<const MCSchedClassDesc *, 16> DelInstrsSC; in preservesResourceLen()
324 ArrayRef<const MCSchedClassDesc *> MSCInsArr = makeArrayRef(InsInstrsSC); in preservesResourceLen()
325 ArrayRef<const MCSchedClassDesc *> MSCDelArr = makeArrayRef(DelInstrsSC); in preservesResourceLen()
DMachineTraceMetrics.cpp109 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI); in getResources()
1202 ArrayRef<const MCSchedClassDesc *> ExtraInstrs, in getResourceLength()
1203 ArrayRef<const MCSchedClassDesc *> RemoveInstrs) const { in getResourceLength()
1210 auto extraCycles = [this](ArrayRef<const MCSchedClassDesc *> Instrs, in getResourceLength()
1214 for (const MCSchedClassDesc *SC : Instrs) { in getResourceLength()
DMachineScheduler.cpp1793 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I); in init()
1874 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
2077 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2306 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
DScheduleDAGInstrs.cpp670 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
/external/llvm/include/llvm/CodeGen/
DTargetSchedule.h44 unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
58 const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;
98 const MCSchedClassDesc *SC = nullptr) const;
122 ProcResIter getWriteProcResBegin(const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
126 ProcResIter getWriteProcResEnd(const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
DMachineTraceMetrics.h269 ArrayRef<const MCSchedClassDesc *> ExtraInstrs = None,
270 ArrayRef<const MCSchedClassDesc *> RemoveInstrs = None) const;
DScheduleDAG.h33 struct MCSchedClassDesc;
255 const MCSchedClassDesc *SchedClass; // NULL or resolved SchedClass.
DScheduleDAGInstrs.h246 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass()
/external/llvm/include/llvm/MC/
DMCSubtargetInfo.h120 const MCSchedClassDesc *SC) const { in getWriteProcResBegin()
124 const MCSchedClassDesc *SC) const { in getWriteProcResEnd()
128 const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC, in getWriteLatencyEntry()
136 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles()
DMCSchedule.h101 struct MCSchedClassDesc { struct
189 const MCSchedClassDesc *SchedClassTable;
219 const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const { in getSchedClassDesc()
/external/llvm/utils/TableGen/
DSubtargetEmitter.cpp45 std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
807 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back(); in GenSchedClassTables()
812 MCSchedClassDesc &SCDesc = SCTab.back(); in GenSchedClassTables()
838 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps; in GenSchedClassTables()
918 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
968 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps; in GenSchedClassTables()
989 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { in GenSchedClassTables()
1110 std::vector<MCSchedClassDesc> &SCTab = in EmitSchedClassTables()
1123 << MCSchedClassDesc::InvalidNumMicroOps in EmitSchedClassTables()
1127 MCSchedClassDesc &MCDesc = SCTab[SCIdx]; in EmitSchedClassTables()
/external/llvm/lib/Target/AArch64/
DAArch64StorePairSuppress.cpp82 const MCSchedClassDesc *SCDesc = in shouldAddSTPToBlock()
/external/llvm/lib/MC/MCDisassembler/
DDisassembler.cpp195 const MCSchedClassDesc *SCDesc = SCModel.getSchedClassDesc(SCClass); in getLatency()