| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ControlFlowFinalizer.cpp | 337 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), in MakeFetchClause() local
341 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
557 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
562 Pair.second.insert(MIb); in runOnMachineFunction()
582 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
586 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
587 DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
596 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
600 DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
601 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 1342 MachineInstr &MIb) const { in checkInstOffsetsDoNotOverlap()
1347 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
1349 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
1354 unsigned Width1 = (*MIb.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
1365 MachineInstr &MIb, in areMemAccessesTriviallyDisjoint() argument
1369 assert((MIb.mayLoad() || MIb.mayStore()) && in areMemAccessesTriviallyDisjoint()
1372 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
1376 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1385 if (isDS(MIb)) in areMemAccessesTriviallyDisjoint()
1386 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
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| D | SIInstrInfo.h | 84 bool checkInstOffsetsDoNotOverlap(MachineInstr &MIa, MachineInstr &MIb) const;
167 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 573 MCInst const &MIb, bool ExtendedB, in isOrderedDuplexPair() argument
580 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
585 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
594 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
608 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
620 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
626 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
627 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
629 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
630 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
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| D | HexagonMCCompound.cpp | 346 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
348 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
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| D | HexagonMCInstrInfo.h | 201 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
238 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
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| /external/honggfuzz/examples/apache-httpd/corpus_http1/ |
| D | 9f77635d8c242affd50ef63913143b2b.000007be.honggfuzz.cov | 9 (>���{E���� �%�������9=�᪅^��C��MIb��U?""ߟ��9 �5T]F����}3�A�lہ��l9s��x�Ƒ���-� �L��O�tJ=�(�2…
11 (>���{E���� �%�������9=�᪅^��C��MIb��U?""ߟ�>0����������������������������������������������������…
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| /external/honggfuzz/examples/apache-httpd/corpus_http2/ |
| D | 9f77635d8c242affd50ef63913143b2b.000007be.honggfuzz.cov | 9 (>���{E���� �%�������9=�᪅^��C��MIb��U?""ߟ��9 �5T]F����}3�A�lہ��l9s��x�Ƒ���-� �L��O�tJ=�(�2…
11 (>���{E���� �%�������9=�᪅^��C��MIb��U?""ߟ�>0����������������������������������������������������…
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 90 MachineInstr &MIb, in areMemAccessesTriviallyDisjoint() argument
93 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
95 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
96 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
109 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
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| D | LanaiInstrInfo.h | 38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 269 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
302 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
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| D | HexagonInstrInfo.cpp | 1627 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint() argument
1631 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
1632 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1637 if (MIa.mayLoad() && !isMemOp(&MIa) && MIb.mayLoad() && !isMemOp(&MIb)) in areMemAccessesTriviallyDisjoint()
1646 unsigned BaseRegB = getBaseAndOffset(&MIb, OffsetB, SizeB); in areMemAccessesTriviallyDisjoint()
2026 const MachineInstr *MIb) const { in isDuplexPair()
2028 HexagonII::SubInstructionGroup MIbG = getDuplexCandidateGroup(MIb); in isDuplexPair()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1427 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1431 assert((MIb.mayLoad() || MIb.mayStore()) &&
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 1075 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, in mayAlias() argument
1078 if (!MIa.mayStore() && !MIb.mayStore()) in mayAlias()
1082 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore()) in mayAlias()
1085 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb); in mayAlias()
1091 for (MachineInstr *MIb : MemInsns) in mayAlias()
1092 if (mayAlias(MIa, *MIb, TII)) in mayAlias()
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| D | AArch64InstrInfo.h | 50 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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| D | AArch64InstrInfo.cpp | 658 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint() argument
665 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
667 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
668 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
677 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 564 MachineInstr *MIb) { in MIsNeedChainEdge() argument
568 assert ((MIa->mayStore() || MIb->mayStore()) && in MIsNeedChainEdge()
572 if (TII->areMemAccessesTriviallyDisjoint(*MIa, *MIb, AA)) in MIsNeedChainEdge()
580 if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand()) in MIsNeedChainEdge()
584 MachineMemOperand *MMOb = *MIb->memoperands_begin(); in MIsNeedChainEdge()
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