| /external/mesa3d/src/mesa/x86/ |
| D | mmx_blend.S | 274 GMB_LOAD( rgba, dest, MM1, MM2 ) ;\
275 GMB_UNPACK( MM1, MM2, MM4, MM5, MM0 ) ;\
276 GMB_ALPHA( MM1, MM3, MM4, MM6 ) ;\
277 GMB_LERP_GSC( MM1, MM2, MM3, MM4, MM5, MM6 ) ;\
295 ONE(MOVD ( REGIND(rgba), MM1 )) /* | | | | qa1 | qb1 | qg1 | qr1 */ ;\
297 ONE(PADDUSB ( MM2, MM1 )) ;\
298 ONE(MOVD ( MM1, REGIND(rgba) )) /* | | | | sa1 | sb1 | sg1 | sr1 */ ;\
300 TWO(MOVQ ( REGIND(rgba), MM1 )) /* qa2 | qb2 | qg2 | qr2 | qa1 | qb1 | qg1 | qr1 */ ;\
301 TWO(PADDUSB ( REGIND(dest), MM1 )) /* sa2 | sb2 | sg2 | sr2 | sa1 | sb1 | sg1 | sr1 */ ;\
302 TWO(MOVQ ( MM1, REGIND(rgba) ))
[all …]
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| D | 3dnow_xform3.S | 75 MOVQ ( MM0, MM1 ) /* x1 | x0 */
81 PUNPCKHDQ ( MM1, MM1 ) /* x1 | x1 */
87 MOVQ ( MM1, MM4 ) /* x1 | x1 */
91 PFMUL ( REGOFF(16, ECX), MM1 ) /* x1*m5 | x1*m4 */
94 PFADD ( MM0, MM1 ) /* x0*m1+x1*m5 | x0*m0+x1*m4 */
97 PFADD ( MM1, MM2 ) /* r1 | r0 */
153 MOVQ ( REGOFF(32, ECX), MM1 ) /* m21 | m20 */
179 PFMUL ( MM1, MM5 ) /* x2*m21 | x2*m20 */
241 MOVD ( REGOFF(8, EAX), MM1 ) /* | x2 */
255 MOVQ ( MM1, MM4 ) /* | x2 */
[all …]
|
| D | 3dnow_xform4.S | 81 MOVQ ( MM0, MM1 ) /* x0 | x0 */
87 PFMUL ( REGOFF(8, ECX), MM1 ) /* x0*m3 | x0*m2 */
103 PFADD ( MM1, MM3 )
161 MOVD ( REGOFF(40, ECX), MM1 ) /* | m22 */
162 PUNPCKLDQ ( REGOFF(56, ECX), MM1 ) /* m32 | m22 */
188 PFMUL ( MM1, MM6 ) /* x3*m32 | x2*m22 */
253 MOVQ ( MM0, MM1 ) /* x1 | x0 */
257 PUNPCKHDQ ( MM1, MM1 ) /* x1 | x1 */
262 PFMUL ( REGOFF(16, ECX), MM1 ) /* x1*m5 | x1*m4 */
266 PFADD ( MM0, MM1 ) /* x0*m1+x1*m5 | x0*m0+x1*m4 */
[all …]
|
| D | 3dnow_xform2.S | 65 MOVD ( REGOFF(4, ECX), MM1 ) /* | m01 */
66 PUNPCKLDQ ( REGOFF(20, ECX), MM1 ) /* m11 | m01 */
84 PFMUL ( MM1, MM7 ) /* x1*m11 | x0*m01 */
202 MOVD ( REGOFF(4, ECX), MM1 ) /* | m01 */
203 PUNPCKLDQ ( REGOFF(20, ECX), MM1 ) /* m11 | m01 */
218 PFMUL ( MM1, MM7 ) /* x1*m11 | x0*m01 */
336 MOVQ ( REGOFF(16, ECX), MM1 ) /* m11 | m10 */
352 PFMUL ( MM1, MM5 ) /* x1*m11 | x1*m10 */
|
| D | 3dnow_xform1.S | 63 MOVQ ( REGOFF(8, ECX), MM1 ) /* m03 | m02 */
77 PFMUL ( MM1, MM5 ) /* x0*m03 | x0*m02 */
398 MOVD ( REGOFF(8, ECX), MM1 ) /* | m02 */
412 PFMUL ( MM1, MM5 ) /* | x0*m02 */
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | 2007-07-03-GR64ToVR64.ll | 4 ; CHECK: movd %rdi, [[MM1:%mm[0-9]+]]
5 ; CHECK: paddusw [[MM0]], [[MM1]]
|
| /external/llvm/test/CodeGen/X86/ |
| D | 2007-07-03-GR64ToVR64.ll | 4 ; CHECK: movd %rdi, [[MM1:%mm[0-9]+]]
5 ; CHECK: paddusw [[MM0]], [[MM1]]
|
| D | ipra-reg-usage.ll | 6 …DR13 DR14 DR15 FP0 FP1 FP2 FP3 FP4 FP5 FP6 FP7 K0 K1 K2 K3 K4 K5 K6 K7 MM0 MM1 MM2 MM3 MM4 MM5 MM6…
|
| /external/autotest/client/cros/cellular/ |
| D | mm1_constants.py | 12 MM1 = '/org/freedesktop/ModemManager1' variable
56 SMS_PATH = MM1 + '/SMS'
|
| /external/autotest/client/cros/networking/ |
| D | mm1_proxy.py | 90 mm1_constants.MM1),
121 mm1_constants.MM1),
|
| /external/autotest/client/cros/cellular/pseudomodem/ |
| D | modemmanager.py | 19 dbus_std_ifaces.DBusObjectManager.__init__(self, bus, mm1_constants.MM1)
|
| D | bearer.py | 28 path = '%s/Bearer/%d' % (mm1_constants.MM1, Bearer.count)
|
| D | sim.py | 120 path = mm1_constants.MM1 + '/SIM/' + str(index)
161 path = mm1_constants.MM1 + '/SIM/' + str(self._index)
|
| D | modem.py | 81 mm1_constants.MM1 + '/Modem/' + str(index), bus, config)
185 path = mm1_constants.MM1 + '/Modem/' + str(self.index)
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrControl.td | 142 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
181 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
217 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
249 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
282 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
|
| D | X86GenRegisterInfo.inc | 85 MM1 = 66,
314 const unsigned MM1_Overlaps[] = { X86::MM1, 0 };
631 { "MM1", MM1_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
920 X86::MM0, X86::MM1, X86::MM2, X86::MM3, X86::MM4, X86::MM5, X86::MM6, X86::MM7,
1182 RI->mapDwarfRegToLLVMReg(42, X86::MM1, false );
1242 RI->mapDwarfRegToLLVMReg(30, X86::MM1, false );
1277 RI->mapDwarfRegToLLVMReg(30, X86::MM1, false );
1308 RI->mapDwarfRegToLLVMReg(42, X86::MM1, true );
1368 RI->mapDwarfRegToLLVMReg(30, X86::MM1, true );
1403 RI->mapDwarfRegToLLVMReg(30, X86::MM1, true );
[all …]
|
| D | X86CallingConv.td | 260 CCAssignToReg<[MM0, MM1, MM2]>>>,
|
| D | X86RegisterInfo.td | 148 def MM1 : Register<"mm1">, DwarfRegNum<[42, 30, 30]>;
|
| /external/ImageMagick/PerlMagick/t/reference/write/composite/ |
| D | CopyBlue.miff | 41 …MM1�MM)�MMF�MM��MM��MM��MMq�MM:�MM<�MM@�MM?�MM=�MM<�MM<�MM1�MM/�MM,�MM.�MM/�MM0�MM3�MM4�MM1�MM-�MM…
|
| /external/autotest/client/site_tests/cellular_ScanningProperty/ |
| D | cellular_ScanningProperty.py | 46 mm1_constants.MM1),
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 198 ENTRY(MM1) \
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86DisassemblerDecoder.h | 208 ENTRY(MM1) \
|
| /external/capstone/arch/X86/ |
| D | X86DisassemblerDecoder.h | 221 ENTRY(MM1) \
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 183 case X86::YMM1: case X86::YMM9: case X86::MM1: in getX86RegNum()
|
| /external/llvm/docs/TableGen/ |
| D | index.rst | 65 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, R10, R10B, R10D, R10W, R11, R11B, R11D,
|