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Searched refs:MachineCSE (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineCSE.cpp39 class MachineCSE : public MachineFunctionPass { class
47 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(5), CurrVN(0) { in MachineCSE() function in __anon18025eaf0111::MachineCSE
101 char MachineCSE::ID = 0;
102 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
106 INITIALIZE_PASS_END(MachineCSE, "machine-cse", in INITIALIZE_PASS_DEPENDENCY()
109 FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); } in INITIALIZE_PASS_DEPENDENCY()
111 bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI, in PerformTrivialCoalescing()
150 MachineCSE::isPhysDefTriviallyDead(unsigned Reg, in isPhysDefTriviallyDead()
190 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI, in hasLivePhysRegDefUses()
217 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, in PhysRegDefsReach()
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/external/llvm/lib/CodeGen/
DMachineCSE.cpp43 class MachineCSE : public MachineFunctionPass { class
51 MachineCSE() : MachineFunctionPass(ID), LookAheadLimit(0), CurrVN(0) { in MachineCSE() function in __anone126a1830111::MachineCSE
109 char MachineCSE::ID = 0;
110 char &llvm::MachineCSEID = MachineCSE::ID;
111 INITIALIZE_PASS_BEGIN(MachineCSE, "machine-cse",
115 INITIALIZE_PASS_END(MachineCSE, "machine-cse", in INITIALIZE_PASS_DEPENDENCY()
122 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI, in INITIALIZE_PASS_DEPENDENCY()
174 MachineCSE::isPhysDefTriviallyDead(unsigned Reg, in isPhysDefTriviallyDead()
215 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI, in hasLivePhysRegDefUses()
265 bool MachineCSE::PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, in PhysRegDefsReach()
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DCMakeLists.txt58 MachineCSE.cpp
/external/llvm/test/CodeGen/SystemZ/
Dint-cmp-51.ll1 ; Check that modelling of CC/CCRegs does not stop MachineCSE from
2 ; removing a compare. MachineCSE will not extend a live range of an
/external/llvm/test/CodeGen/X86/
Dcse-add-with-overflow.ll5 ; MachineCSE should coalesce trivial subregister copies.
7 ; The extra movl+addl should be removed during MachineCSE.
Drdrand.ll49 ; Check that MachineCSE doesn't eliminate duplicate rdrand instructions.
/external/llvm/test/CodeGen/AMDGPU/
Duniform-cfg.ll400 ; uniform. MachineCSE replaces the 2nd condition with the inverse of
/external/swiftshader/third_party/LLVM/
DAndroid.mk96 lib/CodeGen/MachineCSE.cpp \
DBUILD.gn142 "lib/CodeGen/MachineCSE.cpp",
/external/swiftshader/
DCMakeLists.txt272 ${LLVM_DIR}/lib/CodeGen/MachineCSE.cpp
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td2014 // register. MachineCSE skips copies, and we don't want to have to