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Searched refs:Mvn (Results 1 – 24 of 24) sorted by relevance

/external/vixl/test/aarch32/
Dtest-disasm-a32.cc2349 TEST_SHIFT_T32(Mvn, "mvn", 0x0000000a) in TEST()
2376 TEST_WIDE_IMMEDIATE(Mvn, "mvn", 0x0000000e); in TEST()
2378 MUST_FAIL_TEST_BOTH(Mvn(pc, 0xbadbeef), "Ill-formed 'mvn' instruction.\n"); in TEST()
2379 MUST_FAIL_TEST_BOTH(Mvn(eq, pc, 0xbadbeef), in TEST()
3521 COMPARE_T32(Mvn(eq, r4, r6), in TEST()
3525 COMPARE_T32(Mvn(eq, r8, r6), in TEST()
4154 CHECK_T32_16(Mvn(DontCare, r6, r7), "mvns r6, r7\n"); in TEST()
4156 CHECK_T32_16_IT_BLOCK(Mvn(DontCare, eq, r6, r7), in TEST()
Dtest-simulator-cond-rd-operand-const-a32.cc120 M(Mvn) \
Dtest-simulator-cond-rd-operand-const-t32.cc120 M(Mvn) \
Dtest-simulator-cond-rd-operand-rn-t32.cc120 M(Mvn) \
Dtest-simulator-cond-rd-operand-rn-a32.cc120 M(Mvn) \
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc120 M(Mvn) \
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc120 M(Mvn) \
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc120 M(Mvn) \
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc120 M(Mvn) \
Dtest-simulator-cond-rd-operand-rn-shift-rs-a32.cc120 M(Mvn) \
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.cc859 Mvn(rd, rn); in LogicalMacro()
1121 void MacroAssembler::Mvn(const Register& rd, const Operand& operand) { in Mvn() function in vixl::aarch64::MacroAssembler
1128 Mvn(rd, operand.GetImmediate()); in Mvn()
Dmacro-assembler-aarch64.h702 void Mvn(const Register& rd, uint64_t imm) { in Mvn() function
705 void Mvn(const Register& rd, const Operand& operand);
2335 V(mvn, Mvn) \
/external/honggfuzz/examples/apache-httpd/corpus_http2/
D938db24dde426d21080274713126a023.0000c484.honggfuzz.cov39 …����mD�{,��tdW��@_���kQ�!��L���d�gL!Ӕ���z� 5C��M��"+;�,���B���Mvn�o�::�X�MW`�y)*cHd…
165 …����mD�{,��tdW��@_���kQ�!��L���d�gL!Ӕ���z� 5C��M��"+;�,���B���Mvn�o�::�X�MW`�y)*cHd…
202 …����mD�{,��tdW��@_���kQ�!��L���d�gL!Ӕ���z� 5C��M��"+;�,���B���Mvn�o�::�X�MW`�y)*cHd…
D130b09c155802aff6a8d179e27f58071.0001b599.honggfuzz.cov154 …����mD�{,��tdW��@_���kQ�!��L���d�gL!Ӕ���z� 5C��M��"+;�,���B���Mvn�o�::�X�MW`�y)*cHd…
/external/v8/src/arm64/
Dmacro-assembler-arm64.h258 inline void Mvn(const Register& rd, uint64_t imm);
259 void Mvn(const Register& rd, const Operand& operand);
Dmacro-assembler-arm64.cc112 Mvn(rd, rn); in LogicalMacro()
296 void MacroAssembler::Mvn(const Register& rd, const Operand& operand) { in Mvn() function in v8::internal::MacroAssembler
3530 Mvn(scratch, key); in GetNumberHash()
Dmacro-assembler-arm64-inl.h287 void MacroAssembler::Mvn(const Register& rd, uint64_t imm) { in Mvn() function
/external/swiftshader/third_party/subzero/src/
DIceInstARM32.h407 Mvn, enumerator
1055 using InstARM32Mvn = InstARM32UnaryopGPR<InstARM32::Mvn, false>;
DIceInstARM32.cpp3527 template class InstARM32UnaryopGPR<InstARM32::Mvn, false>;
/external/vixl/test/aarch64/
Dtest-assembler-aarch64.cc418 __ Mvn(w0, 0xfff); in TEST() local
419 __ Mvn(x1, 0xfff); in TEST() local
420 __ Mvn(w2, Operand(w0, LSL, 1)); in TEST() local
421 __ Mvn(x3, Operand(x1, LSL, 2)); in TEST() local
422 __ Mvn(w4, Operand(w0, LSR, 3)); in TEST() local
423 __ Mvn(x5, Operand(x1, LSR, 4)); in TEST() local
424 __ Mvn(w6, Operand(w0, ASR, 11)); in TEST() local
425 __ Mvn(x7, Operand(x1, ASR, 12)); in TEST() local
426 __ Mvn(w8, Operand(w0, ROR, 13)); in TEST() local
427 __ Mvn(x9, Operand(x1, ROR, 14)); in TEST() local
[all …]
Dtest-disasm-aarch64.cc201 COMPARE_MACRO(Mvn(w0, Operand(0x101)), "mov w0, #0xfffffefe"); in TEST()
202 COMPARE_MACRO(Mvn(x1, Operand(0xfff1)), "mov x1, #0xffffffffffff000e"); in TEST()
203 COMPARE_MACRO(Mvn(w2, Operand(w3)), "mvn w2, w3"); in TEST()
204 COMPARE_MACRO(Mvn(x4, Operand(x5)), "mvn x4, x5"); in TEST()
205 COMPARE_MACRO(Mvn(w6, Operand(w7, LSL, 12)), "mvn w6, w7, lsl #12"); in TEST()
206 COMPARE_MACRO(Mvn(x8, Operand(x9, ASR, 63)), "mvn x8, x9, asr #63"); in TEST()
5894 COMPARE_MACRO(Mvn(v4.V8B(), v5.V8B()), in TEST()
5897 COMPARE_MACRO(Mvn(v4.V16B(), v5.V16B()), in TEST()
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc1065 __ Mvn(i.OutputRegister(), i.InputOperand(0)); in AssembleArchInstruction() local
1068 __ Mvn(i.OutputRegister32(), i.InputOperand32(0)); in AssembleArchInstruction() local
/external/honggfuzz/examples/apache-httpd/corpus_http1/
Dee4813afd3a732ac3e6c85cd079a0710.000080c5.honggfuzz.cov105 …����mD�{,��tdW��@_���kQ�!��L���d�gL!Ӕ���z� 5C��M��"+;�,���B���Mvn�o�::�X�MW`�y)*cHd…
/external/vixl/src/aarch32/
Dmacro-assembler-aarch32.h2629 void Mvn(Condition cond, Register rd, const Operand& operand) { in Mvn() function
2642 void Mvn(Register rd, const Operand& operand) { Mvn(al, rd, operand); } in Mvn() function
2643 void Mvn(FlagsUpdate flags, in Mvn() function
2649 Mvn(cond, rd, operand); in Mvn()
2661 Mvn(cond, rd, operand); in Mvn()
2666 void Mvn(FlagsUpdate flags, Register rd, const Operand& operand) { in Mvn() function
2667 Mvn(flags, al, rd, operand); in Mvn()