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Searched refs:NEON (Results 1 – 25 of 202) sorted by relevance

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/external/llvm/test/CodeGen/Thumb2/
Daligned-spill.ll2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON
23 ; NEON: f
24 ; NEON: push {r4, r7, lr}
25 ; NEON: sub.w r4, sp, #64
26 ; NEON: bfc r4, #0, #4
28 ; NEON: mov sp, r4
29 ; NEON: vst1.64 {d8, d9, d10, d11}, [r4:128]!
30 ; NEON: vst1.64 {d12, d13, d14, d15}, [r4:128]
36 ; NEON: sub sp, #16
38 ; NEON: add r[[R4:[0-9]+]], sp, #16
[all …]
/external/clang/lib/CodeGen/
DCGBuiltin.cpp2664 { #NameBase, NEON::BI__builtin_neon_ ## NameBase, 0, 0, 0 }
2667 { #NameBase, NEON:: BI__builtin_neon_ ## NameBase, \
2671 { #NameBase, NEON:: BI__builtin_neon_ ## NameBase, \
3281 case NEON::BI__builtin_neon_vcled_s64: in EmitCommonNeonSISDBuiltinExpr()
3282 case NEON::BI__builtin_neon_vcled_u64: in EmitCommonNeonSISDBuiltinExpr()
3283 case NEON::BI__builtin_neon_vcles_f32: in EmitCommonNeonSISDBuiltinExpr()
3284 case NEON::BI__builtin_neon_vcled_f64: in EmitCommonNeonSISDBuiltinExpr()
3285 case NEON::BI__builtin_neon_vcltd_s64: in EmitCommonNeonSISDBuiltinExpr()
3286 case NEON::BI__builtin_neon_vcltd_u64: in EmitCommonNeonSISDBuiltinExpr()
3287 case NEON::BI__builtin_neon_vclts_f32: in EmitCommonNeonSISDBuiltinExpr()
[all …]
/external/llvm/test/CodeGen/ARM/
Darm-interleaved-accesses.ll1 …riple=arm-eabi -mattr=+neon -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NEON
4 ; NEON-LABEL: load_factor2:
5 ; NEON: vld2.8 {d16, d17}, [r0]
16 ; NEON-LABEL: load_factor3:
17 ; NEON: vld3.32 {d16, d17, d18}, [r0]
29 ; NEON-LABEL: load_factor4:
30 ; NEON: vld4.32 {d16, d18, d20, d22}, [r0]!
31 ; NEON: vld4.32 {d17, d19, d21, d23}, [r0]
43 ; NEON-LABEL: store_factor2:
44 ; NEON: vst2.8 {d16, d17}, [r0]
[all …]
Dfp_convert.ll11 ; RUN: | FileCheck %s -check-prefix=NEON
14 ; RUN: | FileCheck %s -check-prefix=NEON
22 ; NEON-LABEL: test1:
23 ; NEON: vadd.f32 [[D0:d[0-9]+]]
24 ; NEON: vcvt.s32.f32 d0, [[D0]]
34 ; NEON-LABEL: test2:
35 ; NEON: vadd.f32 [[D0:d[0-9]+]]
36 ; NEON: vcvt.u32.f32 d0, [[D0]]
46 ; NEON-LABEL: test3:
47 ; NEON: vcvt.f32.u32 d
[all …]
Dfnmscs.ll5 ; RUN: | FileCheck %s -check-prefix=NEON
24 ; NEON-LABEL: t1:
25 ; NEON: vnmla.f32
45 ; NEON-LABEL: t2:
46 ; NEON: vnmla.f32
66 ; NEON-LABEL: t3:
67 ; NEON: vnmla.f64
87 ; NEON-LABEL: t4:
88 ; NEON: vnmla.f64
Dfmscs.ll2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON
10 ; NEON-LABEL: t1:
11 ; NEON: vnmls.f32
26 ; NEON-LABEL: t2:
27 ; NEON: vnmls.f64
Dfnmacs.ll2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON
10 ; NEON-LABEL: t1:
11 ; NEON: vmls.f32
26 ; NEON-LABEL: t2:
27 ; NEON: vmls.f64
Dfmacs.ll2 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s -check-prefix=NEON
12 ; NEON-LABEL: t1:
13 ; NEON: vmla.f32
28 ; NEON-LABEL: t2:
29 ; NEON: vmla.f64
44 ; NEON-LABEL: t3:
45 ; NEON: vmla.f32
Dselect.ll7 ; RUN: | FileCheck %s --check-prefix=CHECK-NEON
82 ; CHECK-NEON-LABEL: f8:
83 ; CHECK-NEON: movw [[R3:r[0-9]+]], #1123
84 ; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
85 ; CHECK-NEON-NEXT: cmp r0, [[R3]]
86 ; CHECK-NEON-NEXT: it eq
87 ; CHECK-NEON-NEXT: addeq{{.*}} [[R2]], #4
88 ; CHECK-NEON-NEXT: ldr
89 ; CHECK-NEON: bx
/external/llvm/test/CodeGen/AArch64/
Daarch64-interleaved-accesses.ll1 ; RUN: llc -mtriple=aarch64 -lower-interleaved-accesses=true < %s | FileCheck %s -check-prefix=NEON
4 ; NEON-LABEL: load_factor2:
5 ; NEON: ld2 { v0.8b, v1.8b }, [x0]
16 ; NEON-LABEL: load_factor3:
17 ; NEON: ld3 { v0.4s, v1.4s, v2.4s }, [x0]
29 ; NEON-LABEL: load_factor4:
30 ; NEON: ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [x0]
42 ; NEON-LABEL: store_factor2:
43 ; NEON: st2 { v0.8b, v1.8b }, [x0]
52 ; NEON-LABEL: store_factor3:
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dfp_convert.ll3 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=NEON
9 ; NEON: test1:
10 ; NEON: vadd.f32 [[D0:d[0-9]+]]
11 ; NEON: vcvt.s32.f32 d0, [[D0]]
21 ; NEON: test2:
22 ; NEON: vadd.f32 [[D0:d[0-9]+]]
23 ; NEON: vcvt.u32.f32 d0, [[D0]]
33 ; NEON: test3:
34 ; NEON: vcvt.f32.u32 d0, d0
44 ; NEON: test4:
[all …]
Dfnmscs.ll2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
11 ; NEON: t1:
12 ; NEON: vnmla.f32
28 ; NEON: t2:
29 ; NEON: vnmla.f32
45 ; NEON: t3:
46 ; NEON: vnmla.f64
62 ; NEON: t4:
63 ; NEON: vnmla.f64
Dfnmacs.ll2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
10 ; NEON: t1:
11 ; NEON: vmls.f32
26 ; NEON: t2:
27 ; NEON: vmls.f64
Dfmscs.ll2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
10 ; NEON: t1:
11 ; NEON: vnmls.f32
26 ; NEON: t2:
27 ; NEON: vnmls.f64
Dselect.ll3 …lc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON
78 ; CHECK-NEON: _f8:
79 ; CHECK-NEON: adr r2, LCPI7_0
80 ; CHECK-NEON-NEXT: movw r3, #1123
81 ; CHECK-NEON-NEXT: adds r1, r2, #4
82 ; CHECK-NEON-NEXT: cmp r0, r3
83 ; CHECK-NEON-NEXT: it ne
84 ; CHECK-NEON-NEXT: movne r1, r2
85 ; CHECK-NEON-NEXT: ldr
86 ; CHECK-NEON: bx
Dfmacs.ll2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
12 ; NEON: t1:
13 ; NEON: vmla.f32
28 ; NEON: t2:
29 ; NEON: vmla.f64
44 ; NEON: t3:
45 ; NEON: vmla.f32
/external/llvm/test/MC/ARM/
Dneon-mov-vfp.s3 …known -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK
4 …known -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK
6 @ The 32-bit variants of the NEON scalar move instructions are also available
14 @ VFP-DAG: error: instruction requires: NEON
15 @ VFP-DAG: error: instruction requires: NEON
16 @ NEON-DAG: vmov.8 d22[5], r2 @ encoding:
17 @ NEON-DAG: vmov.16 d3[2], r4 @ encoding:
26 @ VFP-DAG: error: instruction requires: NEON
27 @ VFP-DAG: error: instruction requires: NEON
28 @ NEON-DAG: vmov.s8 r2, d22[5] @ encoding:
[all …]
Ddiagnostics-noneon.s6 @ CHECK-ERRORS: error: instruction requires: NEON
7 @ CHECK-ERRORS: error: instruction requires: NEON
/external/skqp/site/dev/contrib/
Dsimd.md4 …C++ code as we can from the SSE family of instruction sets on x86 or from NEON on ARM or from MIPS…
6 …rawing routine might be specialized for NEON but not for SSE, or might have a MIPS DSP implementat…
13 …ill write to this interface _once_, which then compiles to efficient SSE, NEON, or portable code (…
20 …NEON is by far the easiest task involved here. Both SSE and NEON naturally work with 128-bit vect…
32 - math written with either SSE or NEON instrinsics is still very hard to read; and
37 …oes nothing, so all `SkNf<N>` recurse down to the default `SkNf<1>`; the NEON backend specializes…
51 … implementations. The 3 `Sk4f` transfermodes replaced portable, SSE, and NEON implementations whi…
58 …NEON and SSE again have some overlap, and they could probably be implemented in terms of each othe…
113 …NEON when working in fixed point is that SSE works most naturally with 4 interlaced pixels at a ti…
115 …NEON backend works with 8 planar pixels, loading them with `vld4_u8` into an `uint8x8x4_t` struct …
[all …]
/external/skia/site/dev/contrib/
Dsimd.md4 …C++ code as we can from the SSE family of instruction sets on x86 or from NEON on ARM or from MIPS…
6 …rawing routine might be specialized for NEON but not for SSE, or might have a MIPS DSP implementat…
13 …ill write to this interface _once_, which then compiles to efficient SSE, NEON, or portable code (…
20 …NEON is by far the easiest task involved here. Both SSE and NEON naturally work with 128-bit vect…
32 - math written with either SSE or NEON instrinsics is still very hard to read; and
37 …oes nothing, so all `SkNf<N>` recurse down to the default `SkNf<1>`; the NEON backend specializes…
51 … implementations. The 3 `Sk4f` transfermodes replaced portable, SSE, and NEON implementations whi…
58 …NEON and SSE again have some overlap, and they could probably be implemented in terms of each othe…
113 …NEON when working in fixed point is that SSE works most naturally with 4 interlaced pixels at a ti…
115 …NEON backend works with 8 planar pixels, loading them with `vld4_u8` into an `uint8x8x4_t` struct …
[all …]
/external/skqp/src/core/
DSkCpu.h43 NEON = 1 << 0, enumerator
98 features |= NEON; in Supports()
102 features |= NEON|NEON_FMA|VFP_FP16; in Supports()
/external/skia/src/core/
DSkCpu.h43 NEON = 1 << 0, enumerator
98 features |= NEON; in Supports()
102 features |= NEON|NEON_FMA|VFP_FP16; in Supports()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td78 // Some single precision VFP instructions may be executed on both NEON and VFP
92 // Some single precision VFP instructions may be executed on both NEON and VFP
140 // Some single precision VFP instructions may be executed on both NEON and
153 // Some single precision VFP instructions may be executed on both NEON and
166 // Some single precision VFP instructions may be executed on both NEON and
209 // Some single precision VFP instructions may be executed on both NEON and
223 // Some single precision VFP instructions may be executed on both NEON and
247 // Some single precision VFP instructions may be executed on both NEON and
261 // Some single precision VFP instructions may be executed on both NEON and
283 // Some single precision VFP instructions may be executed on both NEON and
[all …]
/external/libvpx/libvpx/test/
Dtest_intra_pred_speed.cc264 INTRA_PRED_TEST(NEON, TestIntraPred4, vpx_dc_predictor_4x4_neon,
270 INTRA_PRED_TEST(NEON, TestIntraPred8, vpx_dc_predictor_8x8_neon,
276 INTRA_PRED_TEST(NEON, TestIntraPred16, vpx_dc_predictor_16x16_neon,
283 INTRA_PRED_TEST(NEON, TestIntraPred32, vpx_dc_predictor_32x32_neon,
549 NEON, TestHighbdIntraPred4, vpx_highbd_dc_predictor_4x4_neon,
556 NEON, TestHighbdIntraPred8, vpx_highbd_dc_predictor_8x8_neon,
562 HIGHBD_INTRA_PRED_TEST(NEON, TestHighbdIntraPred16,
572 HIGHBD_INTRA_PRED_TEST(NEON, TestHighbdIntraPred32,
/external/clang/include/clang/Basic/
DTargetBuiltins.h25 namespace NEON {
38 LastNEONBuiltin = NEON::FirstTSBuiltin - 1,
49 LastNEONBuiltin = NEON::FirstTSBuiltin - 1,

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