| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 335 SmallVectorImpl<MachineInstr*> &NewMIs) const{ in StoreRegToStackSlot()
339 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
347 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); in StoreRegToStackSlot()
348 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
355 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) in StoreRegToStackSlot()
363 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); in StoreRegToStackSlot()
364 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) in StoreRegToStackSlot()
370 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) in StoreRegToStackSlot()
375 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) in StoreRegToStackSlot()
383 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) in StoreRegToStackSlot()
[all …]
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| D | PPCInstrInfo.h | 74 SmallVectorImpl<MachineInstr*> &NewMIs) const;
78 SmallVectorImpl<MachineInstr*> &NewMIs) const;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 960 SmallVectorImpl<MachineInstr*> &NewMIs, in StoreRegToStackSlot() argument
968 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
974 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) in StoreRegToStackSlot()
979 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) in StoreRegToStackSlot()
984 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) in StoreRegToStackSlot()
989 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) in StoreRegToStackSlot()
995 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT)) in StoreRegToStackSlot()
1001 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) in StoreRegToStackSlot()
1007 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X)) in StoreRegToStackSlot()
1013 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX)) in StoreRegToStackSlot()
[all …]
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| D | PPCInstrInfo.h | 74 SmallVectorImpl<MachineInstr*> &NewMIs,
79 SmallVectorImpl<MachineInstr *> &NewMIs,
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 957 SmallVector<MachineInstr *, 2> NewMIs; in TryInstructionTransform() local
960 NewMIs)) { in TryInstructionTransform()
964 assert(NewMIs.size() == 2 && in TryInstructionTransform()
967 NewMIs[1]->addRegisterKilled(Reg, TRI); in TryInstructionTransform()
971 mbbi->insert(mi, NewMIs[0]); in TryInstructionTransform()
972 mbbi->insert(mi, NewMIs[1]); in TryInstructionTransform()
974 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] in TryInstructionTransform()
975 << "2addr: NEW INST: " << *NewMIs[1]); in TryInstructionTransform()
978 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in TryInstructionTransform()
979 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in TryInstructionTransform()
[all …]
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| D | MachineLICM.cpp | 1114 SmallVector<MachineInstr *, 2> NewMIs; in ExtractHoistableLoad() local
1118 NewMIs); in ExtractHoistableLoad()
1123 assert(NewMIs.size() == 2 && in ExtractHoistableLoad()
1126 MBB->insert(MI, NewMIs[0]); in ExtractHoistableLoad()
1127 MBB->insert(MI, NewMIs[1]); in ExtractHoistableLoad()
1130 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { in ExtractHoistableLoad()
1131 NewMIs[0]->eraseFromParent(); in ExtractHoistableLoad()
1132 NewMIs[1]->eraseFromParent(); in ExtractHoistableLoad()
1137 UpdateRegPressure(NewMIs[1]); in ExtractHoistableLoad()
1141 return NewMIs[0]; in ExtractHoistableLoad()
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| D | VirtRegRewriter.cpp | 1323 SmallVector<MachineInstr*, 4> NewMIs; in OptimizeByUnfold2() local
1324 if (!TII->unfoldMemoryOperand(MF, &MI, VirtReg, false, false, NewMIs)) in OptimizeByUnfold2()
1326 assert(NewMIs.size() == 1); in OptimizeByUnfold2()
1327 AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI); in OptimizeByUnfold2()
1328 VRM->transferRestorePts(&MI, NewMIs[0]); in OptimizeByUnfold2()
1329 MII = MBB->insert(MII, NewMIs[0]); in OptimizeByUnfold2()
1338 NewMIs.clear(); in OptimizeByUnfold2()
1339 if (!TII->unfoldMemoryOperand(MF, &NextMI, VirtReg, false, false, NewMIs)) in OptimizeByUnfold2()
1341 assert(NewMIs.size() == 1); in OptimizeByUnfold2()
1342 AssignPhysToVirtReg(NewMIs[0], VirtReg, PhysReg, *TRI); in OptimizeByUnfold2()
[all …]
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| D | StackSlotColoring.cpp | 647 SmallVector<MachineInstr*, 4> NewMIs; in UnfoldAndRewriteInstruction() local
648 bool Success = TII->unfoldMemoryOperand(MF, MI, Reg, false, false, NewMIs); in UnfoldAndRewriteInstruction()
651 MachineInstr *NewMI = NewMIs[0]; in UnfoldAndRewriteInstruction()
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| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 1305 SmallVector<MachineInstr *, 2> NewMIs; in tryInstructionTransform() local
1308 /*UnfoldStore=*/false, NewMIs)) { in tryInstructionTransform()
1312 assert(NewMIs.size() == 2 && in tryInstructionTransform()
1315 NewMIs[1]->addRegisterKilled(Reg, TRI); in tryInstructionTransform()
1319 MBB->insert(mi, NewMIs[0]); in tryInstructionTransform()
1320 MBB->insert(mi, NewMIs[1]); in tryInstructionTransform()
1322 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] in tryInstructionTransform()
1323 << "2addr: NEW INST: " << *NewMIs[1]); in tryInstructionTransform()
1326 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
1327 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in tryInstructionTransform()
[all …]
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| D | MachineLICM.cpp | 1178 SmallVector<MachineInstr *, 2> NewMIs; in ExtractHoistableLoad() local
1181 /*UnfoldStore=*/false, NewMIs); in ExtractHoistableLoad()
1186 assert(NewMIs.size() == 2 && in ExtractHoistableLoad()
1190 MBB->insert(Pos, NewMIs[0]); in ExtractHoistableLoad()
1191 MBB->insert(Pos, NewMIs[1]); in ExtractHoistableLoad()
1194 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { in ExtractHoistableLoad()
1195 NewMIs[0]->eraseFromParent(); in ExtractHoistableLoad()
1196 NewMIs[1]->eraseFromParent(); in ExtractHoistableLoad()
1201 UpdateRegPressure(NewMIs[1]); in ExtractHoistableLoad()
1205 return NewMIs[0]; in ExtractHoistableLoad()
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| D | MachinePipeliner.cpp | 232 SmallPtrSet<MachineInstr *, 4> NewMIs; member in __anone7df25700111::SwingSchedulerDAG
907 for (MachineInstr *I : NewMIs) in finishBlock()
909 NewMIs.clear(); in finishBlock()
3391 NewMIs.insert(NewMI); in applyInstrChange()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinInstrInfo.h | 65 SmallVectorImpl<MachineInstr*> &NewMIs) const;
76 SmallVectorImpl<MachineInstr*> &NewMIs) const;
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| D | BlackfinInstrInfo.cpp | 213 SmallVectorImpl<MachineInstr*> &NewMIs) const { in storeRegToAddr()
254 SmallVectorImpl<MachineInstr*> &NewMIs) const { in loadRegFromAddr()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrInfo.h | 236 SmallVectorImpl<MachineInstr*> &NewMIs) const;
249 SmallVectorImpl<MachineInstr*> &NewMIs) const;
288 SmallVectorImpl<MachineInstr*> &NewMIs) const;
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| D | X86InstrInfo.cpp | 2350 SmallVectorImpl<MachineInstr*> &NewMIs) const { in storeRegToAddr()
2361 NewMIs.push_back(MIB); in storeRegToAddr()
2384 SmallVectorImpl<MachineInstr*> &NewMIs) const { in loadRegFromAddr()
2394 NewMIs.push_back(MIB); in loadRegFromAddr()
2882 SmallVectorImpl<MachineInstr*> &NewMIs) const { in unfoldMemoryOperand()
2929 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); in unfoldMemoryOperand()
2933 MachineOperand &MO = NewMIs[0]->getOperand(i); in unfoldMemoryOperand()
2990 NewMIs.push_back(DataMI); in unfoldMemoryOperand()
2999 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); in unfoldMemoryOperand()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 343 SmallVectorImpl<MachineInstr*> &NewMIs) const;
356 SmallVectorImpl<MachineInstr*> &NewMIs) const;
386 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
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| D | X86InstrInfo.cpp | 4779 SmallVectorImpl<MachineInstr*> &NewMIs) const { in storeRegToAddr()
4790 NewMIs.push_back(MIB); in storeRegToAddr()
4814 SmallVectorImpl<MachineInstr*> &NewMIs) const { in loadRegFromAddr()
4824 NewMIs.push_back(MIB); in loadRegFromAddr()
6366 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const { in unfoldMemoryOperand()
6410 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); in unfoldMemoryOperand()
6414 MachineOperand &MO = NewMIs[0]->getOperand(i); in unfoldMemoryOperand()
6470 NewMIs.push_back(DataMI); in unfoldMemoryOperand()
6477 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); in unfoldMemoryOperand()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 207 std::vector<MachineInstr*> NewMIs; in convertToThreeAddress() local
217 NewMIs.push_back(MemMI); in convertToThreeAddress()
218 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
230 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
231 NewMIs.push_back(MemMI); in convertToThreeAddress()
250 MachineInstr *NewMI = NewMIs[j]; in convertToThreeAddress()
263 MFI->insert(MBBI, NewMIs[1]); in convertToThreeAddress()
264 MFI->insert(MBBI, NewMIs[0]); in convertToThreeAddress()
265 return NewMIs[0]; in convertToThreeAddress()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 760 SmallPtrSetImpl<MachineInstr *> &NewMIs,
975 SmallVectorImpl<MachineInstr *> &NewMIs) const { in unfoldMemoryOperand() argument
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 220 std::vector<MachineInstr*> NewMIs; in convertToThreeAddress() local
235 NewMIs.push_back(MemMI); in convertToThreeAddress()
236 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
253 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
254 NewMIs.push_back(MemMI); in convertToThreeAddress()
273 MachineInstr *NewMI = NewMIs[j]; in convertToThreeAddress()
287 MFI->insert(MBBI, NewMIs[1]); in convertToThreeAddress()
288 MFI->insert(MBBI, NewMIs[0]); in convertToThreeAddress()
289 return NewMIs[0]; in convertToThreeAddress()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetInstrInfo.h | 465 SmallVectorImpl<MachineInstr*> &NewMIs) const{ in unfoldMemoryOperand() argument
|