| /external/pcre/dist2/src/ |
| D | pcre2_jit_compile.c | 555 #define OP1(op, dst, dstw, src, srcw) \ macro
1686 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame()
1687 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, SLJIT_IMM, -OVECTOR(0)); in init_frame()
1689 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1702 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), common->mark_ptr); in init_frame()
1703 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, SLJIT_IMM, -common->mark_ptr); in init_frame()
1705 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
1715 OP1(SLJIT_MOV, TMP1, 0, SLJIT_MEM1(SLJIT_SP), OVECTOR(0)); in init_frame()
1716 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, SLJIT_IMM, -OVECTOR(0)); in init_frame()
1718 OP1(SLJIT_MOV, SLJIT_MEM1(STACK_TOP), stackpos, TMP1, 0); in init_frame()
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | fp16-v4-instructions.ll | 6 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
8 ; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
27 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
29 ; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
39 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
41 ; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
51 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
53 ; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
135 ; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
136 ; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
[all …]
|
| D | fp16-v8-instructions.ll | 288 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
291 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
300 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
302 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
340 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
343 ; CHECK-DAG: fcvtn v0.4h, [[OP1]]
352 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
354 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
|
| /external/llvm/test/CodeGen/Hexagon/ |
| D | hwloop4.ll | 5 ; CHECK: [[OP0:r[0-9]+]] = add([[OP1:r[0-9]+]], #-[[OP2:[0-9]+]]
7 ; CHECK: lsr([[OP1]], #{{[0-9]+}})
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600Defines.h | 41 OP1 = (1 << 10), enumerator
|
| D | R600InstrInfo.cpp | 134 return ((TargetFlags & R600_InstFlag::OP1) | in hasInstrModifiers()
|
| /external/boringssl/src/decrepit/cast/ |
| D | cast.c | 90 #define E_CAST(n, key, L, R, OP1, OP2, OP3) \ argument
93 t = (key[n * 2] OP1 R) & 0xffffffff; \
99 L ^= (((((a OP2 b)&0xffffffffL)OP3 c) & 0xffffffffL)OP1 d) & 0xffffffffL; \
|
| /external/kernel-headers/original/uapi/asm-arm64/asm/ |
| D | kvm.h | 192 ARM64_SYS_REG_SHIFT_MASK(op1, OP1) | \
|
| /external/valgrind/none/tests/amd64/ |
| D | fb_test_amd64.c | 449 #define OP1 macro
454 #define OP1 macro
459 #define OP1 macro
464 #define OP1 macro
|
| D | fb_test_amd64.h | 26 #ifdef OP1
|
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | R600MCCodeEmitter.cpp | 133 ((Desc.TSFlags & R600_InstFlag::OP1) || in encodeInstruction()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 658 SDValue OP1; in SelectMul() local
697 OP1 = Sext1; in SelectMul()
709 OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32, in SelectMul()
720 OP0, OP1); in SelectMul()
|
| /external/libevent/ |
| D | whatsnew-2.1.txt | 550 #define OP1 1
|
| /external/llvm/lib/Target/ |
| D | README.txt | 2143 errs() << "OP1 = " << *Op1 << " U=" << Op1->getNumUses() << "\n";
|
| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | README.txt | 2224 errs() << "OP1 = " << *Op1 << " U=" << Op1->getNumUses() << "\n";
|
| /external/toolchain-utils/android_bench_suite/panorama_input/ |
| D | test_008.ppm | 609 7- `OP1 !WBI:%,*�&:%,RAFC17) ��5 #v_e<!*"
|