| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyFrameLowering.cpp | 159 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitPrologue() local
160 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitPrologue()
165 .addReg(OffsetReg); in emitPrologue()
200 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); in emitEpilogue() local
202 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg) in emitEpilogue()
209 .addReg(OffsetReg); in emitEpilogue()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.h | 41 unsigned OffsetReg,
47 unsigned OffsetReg,
246 unsigned OffsetReg) const;
254 unsigned OffsetReg) const;
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| D | R600InstrInfo.cpp | 1059 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1060 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1065 OffsetReg); in expandPostRAPseudo()
1073 unsigned OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); in expandPostRAPseudo() local
1074 if (OffsetReg == AMDGPU::INDIRECT_BASE_ADDR) { in expandPostRAPseudo()
1080 OffsetReg); in expandPostRAPseudo()
1136 unsigned OffsetReg) const { in buildIndirectWrite()
1137 return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); in buildIndirectWrite()
1143 unsigned OffsetReg, in buildIndirectWrite() argument
1154 AMDGPU::AR_X, OffsetReg); in buildIndirectWrite()
[all …]
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| D | SIRegisterInfo.cpp | 293 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in materializeFrameBaseRegister() local
295 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in materializeFrameBaseRegister()
299 .addReg(OffsetReg, RegState::Kill) in materializeFrameBaseRegister()
346 unsigned OffsetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in resolveFrameIndex() local
351 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg) in resolveFrameIndex()
355 .addReg(OffsetReg, RegState::Kill) in resolveFrameIndex()
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| /external/llvm/lib/Target/Lanai/AsmParser/ |
| D | LanaiAsmParser.cpp | 115 unsigned OffsetReg; member
161 return Mem.OffsetReg; in getMemOffsetReg()
600 Op->Mem.OffsetReg = 0; in MorphToMemImm()
608 unsigned OffsetReg = Op->getReg(); in MorphToMemRegReg() local
612 Op->Mem.OffsetReg = OffsetReg; in MorphToMemRegReg()
624 Op->Mem.OffsetReg = 0; in MorphToMemRegImm()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 422 unsigned OffsetReg = 0; in ReduceLoadStore() local
425 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
453 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
456 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); in ReduceLoadStore()
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| D | Thumb2InstrInfo.cpp | 472 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
473 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 212 unsigned OffsetReg; member
271 return Mem.OffsetReg; in getMemOffsetReg()
440 Op->Mem.OffsetReg = offsetReg; in MorphToMEMrr()
449 Op->Mem.OffsetReg = Sparc::G0; // always 0 in CreateMEMr()
461 Op->Mem.OffsetReg = 0; in MorphToMEMri()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 528 unsigned OffsetReg = 0; in ReduceLoadStore() local
532 OffsetReg = MI->getOperand(2).getReg(); in ReduceLoadStore()
567 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); in ReduceLoadStore()
570 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
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| D | Thumb2InstrInfo.cpp | 540 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg(); in rewriteT2FrameIndex() local
541 if (OffsetReg != 0) { in rewriteT2FrameIndex()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringARM32.cpp | 5490 const Variable *OffsetReg, int16_t OffsetRegShAmt, in dumpAddressOpt() argument
5506 if (OffsetReg) in dumpAddressOpt()
5507 OffsetReg->dump(Func); in dumpAddressOpt()
5566 Variable **OffsetReg, int32_t OffsetRegShamt, in matchCombinedBaseIndex() argument
5572 if (*OffsetReg != nullptr) in matchCombinedBaseIndex()
5598 *OffsetReg = Var2; in matchCombinedBaseIndex()
5605 Variable **OffsetReg, OperandARM32::ShiftKind *Kind, in matchShiftedOffsetReg() argument
5614 if (*OffsetReg == nullptr) in matchShiftedOffsetReg()
5616 auto *IndexInst = VMetadata->getSingleDefinition(*OffsetReg); in matchShiftedOffsetReg()
5619 assert(!VMetadata->isMultiDef(*OffsetReg)); in matchShiftedOffsetReg()
[all …]
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonOptAddrMode.cpp | 147 unsigned OffsetReg = MI->getOperand(2).getReg(); in canRemoveAddasl() local
152 if (OffsetReg == RR.Reg) { in canRemoveAddasl()
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| D | HexagonISelLowering.cpp | 2744 unsigned OffsetReg = Hexagon::R28; in LowerEH_RETURN() local
2751 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset); in LowerEH_RETURN()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 715 unsigned OffsetReg = I->getOperand(0).getReg(); in expandEhReturn() local
729 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); in expandEhReturn()
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| D | MipsISelLowering.cpp | 2153 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1; in lowerEH_RETURN() local
2155 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); in lowerEH_RETURN()
2158 DAG.getRegister(OffsetReg, Ty), in lowerEH_RETURN()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 59 unsigned OffsetReg; member in __anon007bec610111::AArch64FastISel::Address
66 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; } in Address()
82 OffsetReg = Reg; in setOffsetReg()
85 return OffsetReg; in getOffsetReg()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 11420 unsigned OffsetReg = 0; in EmitVAARG64WithCustomInserter() local
11477 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); in EmitVAARG64WithCustomInserter()
11478 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) in EmitVAARG64WithCustomInserter()
11488 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
11499 assert(OffsetReg != 0); in EmitVAARG64WithCustomInserter()
11515 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
11526 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 22799 unsigned OffsetReg = 0; in EmitVAARG64WithCustomInserter() local
22854 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); in EmitVAARG64WithCustomInserter()
22855 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) in EmitVAARG64WithCustomInserter()
22865 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
22876 assert(OffsetReg != 0); in EmitVAARG64WithCustomInserter()
22892 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
22903 .addReg(OffsetReg) in EmitVAARG64WithCustomInserter()
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