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Searched refs:OptForSize (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/Target/X86/
DX86FixupBWInsts.cpp138 bool OptForSize; member in __anon806d19160111::FixupBWInstPass
159 OptForSize = MF.getFunction()->optForSize(); in runOnMachineFunction()
290 if (ML->begin() == ML->end() && !OptForSize) { in tryReplaceInstr()
DX86ISelDAGToDAG.cpp158 bool OptForSize; member in __anon8e89e5e80311::X86DAGToDAGISel
165 : SelectionDAGISel(tm, OptLevel), OptForSize(false), in X86DAGToDAGISel()
298 if (!OptForSize) in shouldAvoidImmediateInstFormsForSize()
538 OptForSize = MF->getFunction()->optForSize(); in PreprocessISelDAG()
540 assert((!OptForMinSize || OptForSize) && "OptForMinSize implies OptForSize"); in PreprocessISelDAG()
DX86InstrSSE.td1797 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1813 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1863 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1874 Requires<[UseAVX, OptForSize]>;
1888 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
3289 Requires<[target, OptForSize]>;
3321 let Predicates = [target, OptForSize] in {
3373 let Predicates = [HasAVX, OptForSize] in {
3378 let Predicates = [UseAVX, OptForSize] in {
5155 let Predicates = [UseAVX, OptForSize] in {
DX86InstrInfo.td884 def OptForSize : Predicate<"OptForSize">;
886 def OptForSpeed : Predicate<"!OptForSize">;
DX86InstrAVX512.td5333 Requires<[HasAVX512, OptForSize]>;
6159 (_.EltVT (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512, OptForSize]>;
6179 Requires<[OptForSize]>;
6184 Requires<[OptForSize]>;
DX86InstrCompiler.td274 let Predicates = [OptForSize, NotSlowIncDec, Not64BitMode],
DX86ISelLowering.cpp5834 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize(); in LowerVectorBroadcast() local
5842 if (ConstSplatVal && (Subtarget.hasAVX2() || OptForSize)) { in LowerVectorBroadcast()
5851 (OptForSize && (ScalarSize == 64 || Subtarget.hasAVX2()))) { in LowerVectorBroadcast()
28438 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize(); in combineOr() local
28445 if (!OptForSize && Subtarget.isSHLDSlow()) in combineOr()
/external/llvm/lib/Target/Hexagon/
DHexagonCopyToCombine.cpp102 bool OptForSize);
453 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize); in runOnMachineFunction() local
488 MachineInstr *I2 = findPairable(I1, DoInsertAtI1, OptForSize); in runOnMachineFunction()
491 combine(I1, *I2, MI, DoInsertAtI1, OptForSize); in runOnMachineFunction()
556 bool DoInsertAtI1, bool OptForSize) { in combine() argument
584 bool IsC64 = OptForSize && LoOperand.isImm() && HiOperand.isImm() && in combine()
/external/llvm/lib/Transforms/Vectorize/
DLoopVectorize.cpp1620 VectorizationFactor selectVectorizationFactor(bool OptForSize);
1631 unsigned selectInterleaveCount(bool OptForSize, unsigned VF,
1638 unsigned computeInterleaveCount(bool OptForSize, unsigned VF,
5163 LoopVectorizationCostModel::selectVectorizationFactor(bool OptForSize) { in selectVectorizationFactor() argument
5166 if (OptForSize && Legal->getRuntimePointerChecking()->Need) { in selectVectorizationFactor()
5223 if (MaximizeBandwidth && !OptForSize) { in selectVectorizationFactor()
5245 if (OptForSize) { in selectVectorizationFactor()
5374 unsigned LoopVectorizationCostModel::selectInterleaveCount(bool OptForSize, in selectInterleaveCount() argument
5393 if (OptForSize) in selectInterleaveCount()
6441 bool OptForSize = in processLoop() local
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp156 bool OptForSize; member in __anon55360f140311::X86DAGToDAGISel
163 OptForSize(false) {} in X86DAGToDAGISel()
428 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize); in PreprocessISelDAG()
DX86InstrSSE.td1567 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1578 Requires<[HasSSE2, OptForSize]>;
1597 []>, XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1619 Requires<[HasSSE2, OptForSize]>;
2822 // only in OptForSize mode. It eliminates an instruction, but it also
2828 Requires<[HasSSE1, OptForSize]>;
2900 // See the comments in sse1_fp_unop_s for why this is OptForSize.
2904 Requires<[HasSSE2, OptForSize]>;
3004 Requires<[HasAVX, OptForSize]>;
3009 Requires<[HasAVX, OptForSize]>;
[all …]
DX86InstrInfo.td509 def OptForSize : Predicate<"OptForSize">;
510 def OptForSpeed : Predicate<"!OptForSize">;
DX86ISelLowering.cpp6564 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); in LowerVECTOR_SHUFFLE() local
6593 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) in LowerVECTOR_SHUFFLE()
6595 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) in LowerVECTOR_SHUFFLE()
DX86GenDAGISel.inc32658 /*67642*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasSSE2()) && (OptForSize)
32676 /*67688*/ OPC_CheckPatternPredicate, 31, // (Subtarget->hasSSE2()) && (!OptForSize)
32687 /*67718*/ OPC_CheckPatternPredicate, 32, // (Subtarget->hasAVX()) && (!OptForSize)
38998 /*81310*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasSSE2()) && (OptForSize)
39958 /*83358*/ OPC_CheckPatternPredicate, 39, // (Subtarget->hasSSE1()) && (OptForSize)
39966 /*83377*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasAVX()) && (OptForSize)
39978 /*83408*/ OPC_CheckPatternPredicate, 30, // (Subtarget->hasSSE2()) && (OptForSize)
39986 /*83427*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasAVX()) && (OptForSize)
40168 /*83806*/ OPC_CheckPatternPredicate, 39, // (Subtarget->hasSSE1()) && (OptForSize)
40176 /*83825*/ OPC_CheckPatternPredicate, 40, // (Subtarget->hasAVX()) && (OptForSize)
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